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july, 2008 v0.29p F71863 F71863 super hardware monitor + lpc i/o release date: july, 2008 version: v0.29p
july, 2008 v0.29p F71863 F71863 datasheet revision history version date page revision history 0.10p 2006/04/21 - original version 0.20p 2006/06/14 - release version 0.21p 2006/06/20 - modify typo 0.22p 2006/07/06 - modify typo of register description 0.23p 2006/11/23 - remove gpio17 function of pin66 62 modified the description of wakeup control register 2dh bit 7(spi_cs1_en) 0.24p 2007/7/6 - company readdress 0.25p 2007/8/16 11-18 modify pin names of decription to matche pin configuration 0.26p 2008/1/30 99 modify operating temperature 0.27p 2008/5/2 - update application circuit - modify power type of pwrok pin 0.28p 2008/5/26 - add register descripti on of acpi register f4h/f5h bit7 0.29p 2008/7/21 52 add st1/st2 timing diagram 62 add register of new function( index 29h bit 4-6) 106 update application circuit please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
july, 2008 v0.29p F71863 table of content 1. general description ......................................................................................................... ...............5 2. feature list ................................................................................................................ .....................5 3. key specification........................................................................................................... .................8 4. block diagram ............................................................................................................... .................8 5. pin configuration........................................................................................................... .................8 6. pin description............................................................................................................. ...................9 6.1 power pin .................................................................................................................. ................10 6.2 lpc interface .............................................................................................................. ..............10 6.3 fdc........................................................................................................................ ...................10 6.4 uart and sir ............................................................................................................... ...........11 6.5 parallel port.............................................................................................................. .................13 6.6 hardware monitor........................................................................................................... ..........14 6.7 acpi function pins ......................................................................................................... .........15 6.8 vid controller and others.................................................................................................. ......16 6.9 kbc function ............................................................................................................... ............17 7. function description........................................................................................................ .............18 7.1 power on strapping option.................................................................................................. .....18 7.2 fdc........................................................................................................................ ...................18 7.3 uart....................................................................................................................... .................32 7.4 parallel port.............................................................................................................. .................36 7.5 keyboard contoller......................................................................................................... ..........39 7.6 hardware monitor........................................................................................................... ..........42 7.7 spi interface.............................................................................................................. ................50 7.8 acpi function .............................................................................................................. ............50 7.9 amdsi and intel peci function.............................................................................................. 54 8. register description........................................................................................................ ..............56 8.1 global control registers................................................................................................... ........60 8.2 fdc registers (cr00)....................................................................................................... .......65 8.3 uart1 registers (cr01) ..................................................................................................... ....67 8.4 uart 2 registers (cr02) .................................................................................................... ....68 8.5 parallel port registers (cr03)............................................................................................. .....70 8.6 hardware monitor registers (cr04)........................................................................................72 8.7 kbc registers (cr05) ....................................................................................................... ......87
july, 2008 v0.29p F71863 8.8 gpio registers (cr06) ...................................................................................................... ......88 8.9 vid registers (cr07)....................................................................................................... ........95 8.10 spi registers (cr08)...................................................................................................... ..........97 8.11 pme and acpi registers (cr0a)..........................................................................................100 9. electron characteristic..................................................................................................... ...........103 9.1 absolute maximum ratings ................................................................................................... 103 9.2 dc characteristics ......................................................................................................... .........103 9.3 dc characteristics continued............................................................................................... ..103 10. ordering information ....................................................................................................... ...........105 11. package dimensions ......................................................................................................... ..........105 12. application circuit........................................................................................................ ..............106
july, 2008 v0.29p 5 F71863 1. general description the F71863 is the featured io chip for pc system. equipped with one ieee 1284 parallel port, two uart ports, hardware keyboard controller, serial peripheral interface (spi), sir and one fdc. the F71863 integrated with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate dual current type temp. measurement for cpu thermal diode or external transistors 2n3906. others, the F71863 supports newest amdsi and intel peci interfaces for temperature sensing. for amd platform, the f71883 procides the power sequence controller function. the F71863 provides flexible features for multi-directional application. for instance, supports 4-in and 4-out pins cpu vid controlling with offset implement., provides 25 gpio pins (multi-pin), irq sharing function also designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in measurement of temperature, provides 3 modes fan speed control me chanism included manual mode/stage auto mode/linear auto mode for users? selection. the F71863 also integrated spi interface. the spi interface is for bios usage including bridge function and back up functi on. user can implement bios data in second flash to boot system when primary bios erro r. these features as above description will help you more and improve product value. finally , the F71863 is powered by 3.3v voltage, with the lpc interface in the green package of 128-pqfp. 2. feature list general functions ? comply with lpc spec. 1.0 ? support dpm (device power management), acpi ? support amd power sequence controller ? 4-vidin and 4-vidout for vcore use ? provides one fdc, two uarts, hardware kbc and parallel port ? h/w monitor functions ? spi interface for bios usage ? support amd sid/sic interface and intel peci interface ? 25 gpio pins for flexible application ? 24/48 mhz clock input ? packaged in 128-pqfp and powered by 3.3vcc
july, 2008 v0.29p 6 F71863 fdc ? compatible with ibm pc at disk drive systems ? variable write pre-compensation with track selectable capability ? support vertical recording format ? dma enable logic ? 16-byte data fifos ? support floppy disk drives and tape drives ? detects all overrun and under run conditions ? built-in address mark detection circuit to simplify the read electronics ? completely compatible with industry standard 82077 ? 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate uart ? two high-speed 16c550 compatible uart with 16-byte fifos ? fully programmable serial-interface characteristics ? baud rate up to 115.2k ? support irq sharing infrared ? support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps parallel port ? one ps/2 compatible bi-directional parallel port ? support enhanced parallel port (epp) ? compatible with ieee 1284 specification ? support extended capabilities port (ecp) ? compatible with ieee 1284 specification ? enhanced printer port back-drive current protection keyboard controller ? lpc interface support serial interrupt channel 1, 12. ? two 16bit programmable address fully decoder, default 0x60 and 0x64. ? support two ps/2 interface, one for ps/2 mouse and the other for keyboard. ? keyboard?s scan code support set1, set2. ? programmable compatibility with the 8042. ? support both interrupt and polling modes. ? fast gate a20 and hardware keyboard reset.
july, 2008 v0.29p 7 F71863 hardware monitor functions ? 3 dual current type ( 3 j ) thermal inputs for cpu thermal diode and 2n3906 transistors ? temperature range -40 j ~127 j ? 9 sets voltage monitoring (6 external and 3 internal powers) ? high limit signal (pme#) for vcore level ? 3 fan speed monitoring inputs ? 3 fan speed pwm/dc control outputs(support 3 wire and 4 wire fans) ? stage auto mode ( 2-limit and 3-stage)/linear auto mode/manual mode ? issue pme# and ovt# hardware signals output ? case intrusion detection circuit ? watchdog comparison of all monitored values serial peripheral interface compatible ? support spi bridge function for bios use ? support back up bios function integrate amd si interface integrate intel peci interface support amd power sequence controller package ? 128-pin pqfp green package noted: patented tw207103 tw207104 tw220442 us6788131 b1 twi235231 tw237183 tw235553
july, 2008 v0.29p 8 F71863 3. key specification supply voltage 3.0v to 3.6v operating supply current 10 ma typ. 4. block diagram 5. pin configuration cpu chipset (nb+sb) usb ide spi floppy irda parallel com led(gpio) temperature voltage fan super h/w monitor + i/o F71863 acpi vid controlle r ac?97 kbc amdsi a peci
july, 2008 v0.29p 9 F71863 6. pin description i/o 12t - ttl level bi-directional pin with 12 ma source-sink cap ability. i/ood 12t i/od 16t5v - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. - ttl level bi-directional pi n,open-drain output with 16 ma source-sink capability, 5v tolerance. od 16-u10-5v i/od 12ts5v i lv /o d8-s1 i lv /od 12 o 8-u47-5v - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.). output with 8ma drive and 1ma sink capability. - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.). output with 12ma sink capability. - open-drain pin with 8 ma source-sink capabilit y, pull-up 47k ohms, 5v tolerance. o 8 o 12 - output pin with 8 ma source-sink capability. - output pin with 12 ma source-sink capability.
july, 2008 v0.29p 10 F71863 o 30 - output pin with 30 ma source-sink capability. aout - output pin(analog). od 12 od 12-5v od 24 - open-drain output pin with 12 ma sink capability. - open-drain output pin with 12 ma sink capability, 5v tolerance. - open-drain output pin with 24 ma sink capability. in t5v in ts - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in ts5v - ttl level input pin and schmitt trigger, 5v tolerance. ain - input pin(analog). p - power. 6.1 power pin pin no. pin name type description 4,37,99 vcc p power supply voltage input with 3.3v 68 vsb p stand-by power supply voltage input 3.3v 86 vbat p battery voltage input 88 agnd(d-) p analog gnd 20, 48, 73, 117 gnd p digital gnd 6.2 lpc interface pin no. pin name type pwr description 29 lreset# in ts5v vcc reset signal. it can connect to pcirst# signal on the host. 30 ldrq# o 12 vcc encoded dma request signal. 31 serirq i/o 12t vcc serial irq input/output. 32 lfram# in ts vcc indicates start of a new cycle or termination of a broken cycle. 36-33 lad[3:0] i/o 12t vcc these signal lines commun icate address, control, and data information over the lpc bus between a host and a peripheral. 38 pciclk in ts vcc 33mhz pci clock input. 39 clkin in ts vcc system clock input. according to the input frequency 24/48mhz. 6.3 fdc pin no. pin name type pwr description 7 densel# od 24 vcc drive density select. set to 1 - high data rate.(500kbps, 1mbps) set to 0 ? low data rate. (250kbps, 300kbps) 8 moa# od 24 vcc motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. 9 drva# od 24 vcc drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. 10 wdata# od 24 vcc write data. this logic low open drain writes pre-compensation serial data to the selected fdd. an
july, 2008 v0.29p 11 F71863 open drain output. 11 dir# od 24 vcc direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion 12 step# od 24 vcc step output pulses. this active low open drain output produces a pulse to move the head to another track. 13 hdsel# od 24 vcc head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 14 wgate# od 24 vcc write enable. an open drain output. 15 rdata# in ts5v vcc the read data input signal from the fdd. 16 trk0# in ts5v vcc track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. 17 index# in ts5v vcc this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. 18 wpt# in ts5v vcc write protected. this active low schmitt input from the disk drive indicates that the diskette is write-protected. 19 dskchg# in ts5v vcc diskette change. this signal is active low at power on and whenever the diskette is removed. 6.4 uart and sir pin no. pin name type pwr description irtx o 12 infrared transmitter output. 27 gpio42 i/ood 12t vcc general purpose io irrx in ts infrared receiver input. 28 gpio43 i/ood 12t vsb general purpose io. 118 dcd1# in t5v vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 119 ri1# in t5v vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 120 cts1# in t5v vcc clear to send is the modem control input. dtr1# o 8-u47,5v uart 1 data terminal ready. an active low signa l informs the modem or data set that controller is ready t o communicate. internal 47k ohms pulled high and disabl e after power on strapping. 121 fan60_100 in t5v vcc power on strapping pin: 1(default): (internal pull high) power on fan speed default duty is 60%.(pwm) 0: (external pull down) power on fan speed default duty is 100%.(pwm) 122 rts1# o 8-u47,5v vcc uart 1 request to send. an active low signal inform s the modem or data set that the controller is ready t o send data. internal 47k ohms pulled high and disabl e
july, 2008 v0.29p 12 F71863 after power on strapping. 123 dsr1# in t5v vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. sout1 o 8-u47,5v uart 1 serial output. used to transmit serial data ou t to the communication link. internal 47k ohms pulled hig h and disable after power on strapping. 124 config4e_2e in t5v vcc power on strapping: 1(default) configuration register:4e 0 configuration register:2e 125 sin1 in t5v vcc serial input. used to receive serial data through th e communication link. 126 dcd2# in t5v vcc data carrier detect. an active low signal indicates th e modem or data set has detected a data carrier. 127 ri2# in t5v vcc ring indicator. an active low signal indicates that a rin g signal is being received from the modem or data set. 128 cts2# in t5v vcc clear to send is the modem control input. dtr2# o 8-u47,5v uart 2 data terminal ready. an active low signa l informs the modem or data set that controller is ready t o communicate. internal 47k ohms pulled high and disabl e after power on strapping. 1 fwh_trap in t5v vcc power on strapping : 1(default): spi as a backup bios 0 : spi as a primary bios rts2# o 8-u47,5v uart 2 request to send. an active low signal inform s the modem or data set that the controller is ready t o send data. internal 47k ohms pulled high and disabl e after power on strapping. 2 pwm_dc in t5v vcc power on strapping : 1 (default): fan control method will be pwm mode 0 drive :fan control method will be dac mode 3 dsr2# in t5v vcc data set ready. an active low signal indicates th e modem or data set is ready to establish a communication link and transfer data to the uart. sout2 o 8-u47,5v uart 2 serial output. used to transmit serial data ou t to the communication link. internal 47k ohms pulle d high and disable after power on strapping. 5 spi_trap in t5v vcc power on strapping: 1(default) : spi function disable 0 : spi function enable 6 sin2 in t5v vcc serial input. used to receive serial data through th e communication link.
july, 2008 v0.29p 13 F71863 66 cpu_pwrgd vsb 6.5 parallel port pin no. pin name type pwr description 100 slct in ts5v vcc an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 101 pe in ts5v vcc an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 102 busy in ts5v vcc an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 103 ack# in ts5v vcc an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 104 slin# od 12-5v vcc output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 105 init# od 12-5v vcc output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 106 err# in ts5v vcc an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 107 afd# od 12-5v vcc an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 108 stb# od 12-5v vcc an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 109 pd0 i/o 12ts5v vcc parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 110 pd1 i/o 12ts5v vcc parallel port data bus bit 1. 111 pd2 i/o 12ts5v vcc parallel port data bus bit 2. 112 pd3 i/o 12ts5v vcc parallel port data bus bit 3. 113 pd4 i/o 12ts5v vcc parallel port data bus bit 4. 114 pd5 i/o 12ts5v vcc parallel port data bus bit 5.
july, 2008 v0.29p 14 F71863 115 pd6 i/o 12ts5v vcc parallel port data bus bit 6. 116 pd7 i/o 12ts5v vcc parallel port data bus bit 7. 6.6 hardware monitor pin no. pin name type pwr description 93 vin6 ain vcc voltage input 6. 94 vin5 ain vcc voltage input 5. 95 vdimm(vin4) ain vcc voltage input for vdimm dual str (2.5v/1.8v). 96 vdda(vin3) ain vcc voltage input for vdda (2.5v). 97 vldt(vin2) ain vcc voltage input for vldt (1.2v). 98 vcore(vin1) ain vcc voltage input for vcore. 21 fanin1 in ts5v vcc fan 1 tachometer input. 22 fanctl1 od 12-5v aout vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. 23 fanin2 in ts5v vcc fan 2 tachometer input. 24 fanctl2 od 12-5v aout vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. fanin3 in ts5v fan 3 speed input. 25 gpio40 i/ood 12t vcc general purpose io. fanctl3* od 12-5v aout fan 3 control output. this pin provides pwm duty-cycle output or a voltage output. *this pin default function is fanctl (pwm signal output), please take care the application if user want to implement gpio function. 26 gpio41 i/ood 12t vcc general purpose io. 89 d3+(system) ain vcc thermal diode/trans istor temperature sensor input for system use. 90 d2+ ain vcc thermal diode/transistor temperature sensor input. 91 d1+(cpu) ain vcc cpu thermal di ode/transistor temperature sensor input. this pin is for cpu use. 92 vref aout vcc voltage sensor output. pme# od 12-5v generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state. 79 gpio25 i/ood 12t vsb general purpose io. gpio10 i/ood 12t general purpose io. 59 spi_slk o 12 vsb serial clock output pin for spi device. gpio11 i/ood 12t general purpose io. 60 spi_cs0# o 12 vsb function a: when using firmware hub bios for primary bios and spi bios for second bios, please connect this pin to spi bios chip select pin. function b: when using two spi flashes for primary and back up bios, please connect this pin to primary bios chip select pin. 61 gpio12 i/ood 12t vsb general purpose io.
july, 2008 v0.29p 15 F71863 spi_miso in t5v spi master in/slave out pin. fanctl1_1 od 12-5v fan 1 control output. this pin provides pwm duty-cycle open drain output for intel 4-pin fan. gpio13 i/ood 12t general purpose io. spi_mosi o 12 spi master out/slave in pin. 62 beep od 24 vsb beep pin. gpio14 i/ood 12t general purpose io. fwh_dis o 12 firmware hub disable wdtrst# od 12-5v watch dog timer signal output. 63 spi_cs1# o 12 vsb when using two spi flashes for primary and back up bios, please connect this pin to back up bios chip select pin. 67 ovt# od 12-5v vsb over temperature signal output. 6.7 acpi function pins pin no. pin name type pwr description gpio15 i/ood 12t general purpose io. led_vsb od 12 power led for vsb. 64 alert# od 12 vsb alert a signal when temperature over limit setting. gpio16 i/ood 12t general purpose io. 65 led_vcc od 12 vsb power led for vcc. pcirst1# od 12 it is a output buffer of lreset#. 74 gpio20 i/ood 12 vsb general purpose io. pcirst2# o 12 it is a output buffer of lreset#. 75 gpio21 i/ood 12 vsb general purpose io. pcirst3# o 12 it is a output buffer of lreset#. 76 gpio22 i/ood 12 vsb general purpose io. 77 s5# in ts5v vsb s5# signal input. atxpg_in ain atx power good input. 78 gpio24 i/ood 12t vsb general purpose io. pwrok od 12 pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. 84 gpio32 i/ood 12t vbat general purpose io. pwsin# in ts5v vsb main power switch button input. 80 gpio26 i/ood 12t general purpose io. pwsout# od 12 panel switch output. this pin is low active and pulse output. it is power on request output#. 81 gpio27 i/ood 12t vsb general purpose io. s3# in ts5v s3# input is main power on-off switch input. 82 gpio30 i/ood 12t vsb general purpose io. 83 ps_on# od 12-5v vsb power supply on-off control output. connect to atx power supply ps_on# signal.
july, 2008 v0.29p 16 F71863 gpio31 i/ood 12t general purpose io. rsmrst# od 12 resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.3v. 85 gpio33 i/ood 12t vbat general purpose io. 87 copen# in ts5v vbat case open detection #. this pin is connected to a specially designed low power cmos flip-flop backed by the battery for case open state preservation during power loss. 6.8 vid controller and others pin no. pin name type pwr description 45-42 vidin[d:a] in ts5v vcc cpu vid input pins. special level input vih ? 0.9, vil ? 0.6 52-49 vidout[d:a] od 12 vsb cpu vid output pins. 46 vcore_en od 12 vcc active high. the function of this pin is to enable the pwm for cpu vcore. the external pull high resistor is required. 47 vldt_en od 12 vcc active high. the function of this pin is to enable the vldt voltage. the external pull high resistor is required. 53 vdda_en od 12 vsb active high. the function of this pin is to enable the vdda power for amd k8 and after cpu. the external pull high resistor is required. 54 vdimm_en od 12 vsb active high. the function of this pin is to enable the pwm for vdimm_str dual voltage. the external pull high resistor is required. st2 od 12 status pin2 for s0#/s3#/s 5# states application. in s0# ? st2 pin status is tri-state. in s3# ? st2 pin status is low level. in s5# ? st2 pin status is low level, and can be programmed to tri-state. slotocc# in ts5v cpu slotocc# input. 55 gpio02 i/ood 12t vsb general purpose pin. st1 od 12 status pin1 for s0#/s3#/ s5# states application. in s0# ? st1 pin status is tri-state. in s3# ? st1 pin status is low level. in s5# ? st1 pin status is tri-state. gpio03 i/ood 12t general purpose pin. 56 wdtrst# od 12-5v vsb watch dog timer signal output. 57 amdsi_clk od 12 vsb amdsi interface clock output. peci i lv /o d8-s1 intel peci hardware monitor interface. 58 amdsi_dat_1 i lv /od 12 vsb amdsi interface data input.
july, 2008 v0.29p 17 F71863 6.9 kbc function pin no. pin name type pwr description 40 kbrst# o d 16-u10,5v vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) 41 ga20 o d 16-u10,5v vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) 69 kdata i/od 16t,5v vsb keyboard data. 70 kclk i/od 16t,5v vsb keyboard clock. 71 mdata i/od 16t,5v vsb ps2 mouse data. 72 mclk i/od 16t,5v vsb ps2 mouse clock.
july, 2008 v0.29p 18 F71863 7. function description 7.1 power on strapping option the F71863 provides four pins for power on hardware strapping to select functions. there is a form to describe how to set the functions you want. pin no. symbol value description 1 spi as a backup bios (default) 1 fwh_trap 0 spi as a primary bios 1 fan control mode: pwm mode. ( default) 2 pwm_dc 0 fan control mode: linear mode. 1 spi function disable (default) 5 spi_trap 0 spi function enable 1 power on fan speed default duty is 60%(pwm)(default) 121 fan60_100 0 power on fan speed default duty is 100%(pwm) 1 configuration register i/o port is 4e/4f. (default) 124 config4e_2e 0 configuration register i/o port is 2e/2f. 7.2 fdc the floppy disk controller provides the interface between a host processor and one floppy disk drives. it integrates a controller and a digital data separator with write pre-compensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, and 1 mbps. it operates in pc/at mode and supports 3-mode type drives. the fdc configuration is handled by software and a set of configuration registers. status, data, and control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the fdc. these configuration registers can select the data rate, enable interrupts, drives, and dma modes, and indicate errors in the data or operation of the fdc/fdd. the controller manages data transfers using a set of data transfer and control commands. these commands are handled in three phases: command, execution, and result. not all commands utilize all these three phases. the below content is about the fdc device register descriptions. all the registers are for software porting reference.
july, 2008 v0.29p 19 F71863 status register a (ps/2 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed. 5 step r 0 this bit indicates the complement of step# disk interface output. 4 trk0_n r - this bit indicates the state of trk0# disk interface input. 3 hdsel r 0 this bit indicates the complement of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index_n r - this bit indicates the state of index# disk interface input. 1 wpt_n r - this bit indicates the state of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir r 0 this bit indicates the comp lement of dir# disk interface output. status register a (model 30 mode) ? base + 0 bit name r/w default description 7 intpend r 0 this bit indicates the state of the interrupt output. 6 drq r 0 this bit indicates the state of the drq signal. 5 step_ff r 0 this bit indicates the complement of latched step# disk interface output. 4 trk0 r - this bit indicates the complement of trk0# disk interface input. 3 hdsel_n r 1 this bit indicates the state of hdsel# disk interface output. 0: side 0. 1: side 1. 2 index r - this bit indicates the comp lement of index# disk interface input. 1 wpt r - this bit indicates the complement of wpt# disk interface input. 0: disk is write-protected. 1: disk is not write-protected. 0 dir_n r 1 this bit indicates the state of dir# disk interface output. 0: head moves in inward direction. 1: head moves in outward direction. status register b (ps/2 mode) ? base + 1 bit name r/w default description 7-6 reserved r 11 reserved. return 11b when read. 5 dr0 r 0 drive select 0. this bit reflec ts the bit 0 of digital output register. 4 wdata r 0 this bit changes state at every rising edge of wdata#. 3 rdata r 0 this bit changes state at every rising edge of rdata#. 2 wgate r 0 this bit indicates the complement of wgate# disk interface output. 1 moten1 r 0 this bit indicates the complement of mob# disk interface output. not support in this design.
july, 2008 v0.29p 20 F71863 0 moten0 r 0 this bit indicates the comp lement of moa# disk interface output. status register b (model 30 mode) ? base + 1 bit name r/w default description 7 drv2_n r - 0: a second drive has been installed. 1: a second drive has not been installed. 6 dsb_n r 1 this bit indicates the state of dr vb# disk interface output. not support in this design. 5 dsa_n r 1 this bit indicates the state of drva# disk interface output. 4 wdata_ff r 0 this bit is latched at the rising edge of wdata# and is cleared by a read from the digital input register. 3 rdata_ff r 0 this bit is latched at the rising edge of rdata# and is cleared by a read form the digital input register. 2 wgate_ff r 0 this bit is latched at the falling edge of wgate# and is cleared by a read from the digital input register. 1 dsd_n r 1 this bit indicates the complem ent of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complem ent of drvc# disk interface output. not support in this design. digital output register ? base + 2 bit name r/w default description 7 moten3 r 0 motor enable 3. not support in this design. 6 moten2 r 0 motor enable 2. not support in this design. 5 moten1 r/w 0 motor enable 1. used to control mob#. mob# is not sup port in this design. 4 moten0 r/w 0 motor enable 0. used to control moa#. 3 damen r/w 0 dma enable. this bit has two mode of operation. pc-at and model 30 mode: write 1 will enable dma and irq, write 0 will disable dma and irq. ps/2 mode: this bit is reserved. dma and irq are always enabled in ps/2 mode. 2 reset r 0 write 0 to this bit will reset the controller. i will remain in reset condition until a 1 is written. 1 dsd_n r 1 this bit indicates the complem ent of drvd# disk interface output. not support in this design. 0 dsc_n r 1 this bit indicates the complem ent of drvc# disk interface output. not support in this design. tape drive register ? base + 3 bit name r/w default description 7-6 reserved r 00 reserved. return 00b when read. 5-4 typeid r 11 reserved in normal function, return 11b when read. if 3 mode fdd function is enabled. these bits indicate the drive type id.
july, 2008 v0.29p 21 F71863 3-2 reserved r 11 reserved. return 11b when read in normal function. return 00b when read in 3 mode fdd function. 1-0 tapesel r/w 0 these bits assign a logical drive number to be a tape drive. main status register ? base + 4 bit name r/w default description 7 rqm r 0 request for master indicates that t he controller is ready to send or receive data from the up through the fifo. 6 dio r 0 data i/o (direction): 0: the controller is expecting a byte to be written to the data register. 1: the controller is expecting a byte to be read from the data register. 5 non_dma r 0 non dma mode: 0: the controller is in dam mode. 1: the controller is interrupt or software polling mode. 4 fdc_busy r 0 this bit indicate that a read or write command is in process. 3 drv3_busy r 0 fdd number 3 is in seek or calibration condition. fdd number 3 is not support in this design. 2 drv2_busy r 0 fdd number 2 is in seek or calibration condition. fdd number 2 is not support in this design. 1 drv1_busy r 0 fdd number 1 is in seek or calibration condition. fdd number 1 is not support in this design. 0 drv0_busy r 0 fdd number 0 is in seek or calibration condition. data rate select register ? base + 4 bit name r/w default description 7 softrst w 0 a 1 written to this bit will softwa re reset the controller. auto clear after reset. 6 pwrdown w 0 a 1 to this bit will put the controller into low power mode which will turn off the oscillator and data separator circuits. 5 reserved - - return 0 when read. 4-2 precomp w 000 select the valu e of write precompensation: 250k-1mbps 2mbps 000: default delays default delays 001: 41.67ns 20.8ns 010: 83.34ns 41.17ns 011: 125.00ns 62.5ns 100: 166.67ns 83.3ns 101: 208.33ns 104.2ns 110: 250.00ns 125.00ns 111: 0.00ns (disabled) 0.00ns (disabled) the default value of corresponding data rate: 250kbps: 125ns 300kbps: 125ns 500kbps: 125ns 1mbps: 41.67ns 2mbps: 20.8ns 1-0 drate w 10 data rate select: mfm fm 00: 500kbps 250kbps 01: 300kbps 150kbps 10: 250kbps 125kbps 11: 1mbps illegal
july, 2008 v0.29p 22 F71863 data (fifo) register ? base + 5 bit name r/w default description 7-0 data r/w 00h the fifo is used to transfer all commands, data and status between controller and the system. the data register consists of four status registers in a stack with only one register presented to the data bus at a time. the fifo is default disabled and could be enabled via the configure command. status registers 0 bit name r/w default description 7-6 ic r - interrupt code : 00: normal termination of command. 01: abnormal termination of command. 10: invalid command. 11: abnormal termination caused by poling. 5 se r - seek end. set when a seek or recalibrate or a read or write with implied seek command is completed. 4 ec r - equipment check. 0: no error 1: when a fault signal is received form the fdd or the trk0# signal fails to occur after 77 step pulses. 3 nr r - not ready. 0: drive is ready 1: drive is not ready. 2 hd r - head address. the current head address. 1-0 ds r - drive select. 00: drive a selected. 01: drive b selected. 10: drive c selected. 11: drive d selected. status registers 1 bit name r/w default description 7 en r - end of track. set when the fdc tries to access a sector beyond the final sector of a cylinder. 6 de r - data error. the fdc detect a crc error in either the id field or the data field of a sector. 4 or r - overrun/underrun. set when the fdc is not serviced by the host system within a certain time interval during data transfer. 3 reserved - - unused. this bit is always ?0?
july, 2008 v0.29p 23 F71863 2 nd r - no data. set when the following conditions occurred: 1. the specified sector is not found during any read command. 2. the id field cannot be read without errors during a read id command. 3. the proper sector sequence cann ot be found during a read track command. 1 nw r - no writable set when wpt# is active during execution of write commands. 0 ma r - missing address mark. set when the following conditions occurred: 1. cannot detect an id address mark at the specified track after encountering the index pulse form the index# pin twice. 2. cannot detect a data address mark or a deleted data address mark on the specified track. status registers 2 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 cm r - control mark. set when following conditions occurred: 1. encounters a deleted data address mark during a read data command. 2. encounters a data address mark during a read deleted data command. 5 dd r - data error in data field. the fdc detects a crc error in the data field. 4 wc r - wrong cylinder. set when the track address from the sector id field is different from the track address maintained inside the fdc. 3 se r - scan equal. set if the equal condition is satisfied during execution of the scan command. 2 sn r - scan not satisfied. set when the fdc cannot find a sector on the track which meets the desired condition during any scan command. 1 bc r - bad cylinder. the track address from the sector id fi eld is different from the track address maintained inside the fdc and is equal to ffh which indicates a bad track. 0 md r - missing data address mark. set when the fdc cannot detect a data address mark or a deleted data address mark. status registers 3 bit name r/w default description 7 reserved - - unused. this bit is always ?0?. 6 wp r - write protect. indicates the status of wpt# pin. 5 reserved r - unused. this bit is always ?1?.
july, 2008 v0.29p 24 F71863 4 t0 r - track 0. indicates the status of the trk0# pin. 3 reserved. r - unused. this bit is always ?1?. 2 hd r - head address. indicates the status of the hdsel# pin. 1 ds1 r - 0 ds0 r - drive select. these two bits indicate the ds1, ds0 bits in the command phase. digital input register (pc-at mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-0 reserved r - reserved. digital input register (ps/2 mode) ? base + 7 bit name r/w default description 7 dskchg r - this bit indicates the complement of dskchg# disk interface input. 6-3 reserved - - reserved. 2-1 drate r 10 these bits indicate the status of the drate programmed through the data rate select register or co nfiguration control register. 0 highden_n r 1 0: 1mbps or 500kbps data rate is chosen. 1: 300kbps or 250kbps data rate is chosen. digital input register (model 30 mode) ? base + 7 bit name r/w default description 7 dskchg_n r - this bit indicates the state of dskchg# disk interface input. 6-4 reserved - - reserved. 3 dmaen r 0 this bit reflects the dma bit in digital output register. 2 nopre r 0 this bit reflects the nopre bit in configuration control register. 1-0 drate r 10 these bits indicate the status of drate programmed through the data rate select register or config uration control register. configuration control register (pc-at and ps/2 mode) ? base + 7 bit name r/w default description 7-2 reserved - - reserved. 1-0 drate w 10 these bit determine the data rate of the floppy controller. see drate bits in data rate select register.
july, 2008 v0.29p 25 F71863 configuration control register (model 30 mode) ? base + 7 bit name r/w default description 7-3 reserved - - reserved. 2 nopre w 0 this bit could be programmed thr ough configuration control register and be read through the bit 2 in digital input r egister in model 30 mode. but it has no functionality. 1-0 drate w 10 these bit determine the data rate of the floppy controller. see drate bits in data rate select register. fdc commands terminology: c cylinder number 0 -256 d data pattern dir step direction 0: step out 1: step in ds0 drive select 0 ds1 drive select 1 dtl data length ec enable count eot end of track efifo enable fifo 0: fifo is enabled. 1: fifo is disabled. eis enable implied seek fifothr fifo threshold gap alters gap length gpl gap length h/hds head address hlt head load time hut head unload time lock lock efifo, fifothr, ptrtrk bits. prevent these bits from being affected by software reset. mfm mfm or fm mode 0: fm 1: mfm mt multi-track n sector size code. all values up to 07h are allowable. 00: 128 bytes 01: 256 bytes .. .. 07 16 kbytes ncn new cylinder number nd non-dma mode ow overwritten pcn present cylinder number poll polling disable 0: polling is enabled. 1: polling is disabled. pretrk precompensation start track number r sector address rcn relative cylinder number
july, 2008 v0.29p 26 F71863 sc sector per cylinder sk skip deleted data address mark srt step rate time st0 status register 0 st1 status register 1 st2 status register 2 st3 status register 3 wgate write gate alters timing of we. read data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 0 1 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 0 1 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- sector id information prior to command execution
july, 2008 v0.29p 27 F71863 w ---------------------------- dtl -------------------------- execution data transfer between the fdd and system result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 0 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. fdd reads contents of all cylinders from index hole to eot. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 0 1 0 command code w 0 0 0 0 0 hds ds1 ds0
july, 2008 v0.29p 28 F71863 execution the first correct id information on the cylinder is stored in data register. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- disk status after the command has been completed. verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm sk 1 0 1 1 0 command code w ec 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w -------------------------- dtl/sc ------------------------ sector id information prior to command execution execution no data transfer result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller
july, 2008 v0.29p 29 F71863 write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm 0 0 0 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. write deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w mt mfm 0 0 1 0 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ----------------------------- c --------------------------- w ----------------------------- h --------------------------- w ----------------------------- r --------------------------- w ------------------------------ n --------------------------- w ---------------------------- eot -------------------------- w ---------------------------- gpl -------------------------- w ---------------------------- dtl -------------------------- sector id information prior to command execution execution data transfer between the fdd and system. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- status information after command
july, 2008 v0.29p 30 F71863 r ---------------------------- st2 -------------------------- execution. r ----------------------------- c --------------------------- r ----------------------------- h --------------------------- r ----------------------------- r --------------------------- r ----------------------------- n --------------------------- sector id information after command execution. format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 mfm 0 0 1 1 0 1 command code w 0 0 0 0 0 hds ds1 ds0 w ------------------------------ n --------------------------- bytes/sector w ---------------------------- sc -------------------------- sectors/cylinder w ---------------------------- gpl -------------------------- gap 3 length w ----------------------------- d --------------------------- data pattern ------------------------------ c --------------------------- w ------------------------------ h --------------------------- w ------------------------------ r --------------------------- execution for each sector ( repeat ) w ----------------------------- n -------------------------- input sector parameter. result r ---------------------------- st0 -------------------------- r ----------------------------- st1 -------------------------- r ---------------------------- st2 -------------------------- status information after command execution. r ------------------------- undefined ---------------------- r ------------------------- undefined ---------------------- r -------------------------- undefined ----------------------- r ------------------------- undefined ---------------------- recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 1 1 command code w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 0 0 0 command code result r ---------------------------- st0 -------------------------- r ---------------------------- pcn --------------------------
july, 2008 v0.29p 31 F71863 specify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 0 1 1 command code w |------------------ srt -------------------| |------------------ hut -------------------| w |------------------------------------- srt ---------------------------------------| nd seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w ---------------------------- ncn -------------------------- execution head positioned over proper cylinder on diskette configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w 0 eis efifo poll |---------------- fifothr ---------------| w ---------------------------- pretrk -------------------------- execution internal registers written relative seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 1 dir 0 0 1 1 1 1 command code w 0 0 0 0 0 hds ds1 ds0 w ---------------------------- rcn -------------------------- perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d0 gap wgate lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0
july, 2008 v0.29p 32 F71863 dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 1 1 1 0 command code result r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r -------------------------- pcn ( drive 0 ) ------------------------ r |------------------ srt -------------------| |------------------ hut -------------------| r |------------------------------------- srt ---------------------------------------| nd r -------------------------- sc/eot ------------------------ r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll |---------------- fifothr ---------------| r ---------------------------- pretrk -------------------------- sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------------------- st3 -------------------------- status information abut disk drive invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remark command w ---------------------------- invalid codes -------------------------- fdc goes to standby state. result r ---------------------------- st0 -------------------------- st0 = 80h 7.3 uart the F71863 provides two uart ports and supports irq sharing for system application. the uarts are used to convert data between parallel format and serial format. they convert parallel data into serial format on transmission and serial format into parallel data on receiver side. the serial format is formed by one start bit, followed by five to eight data bits, a parity bit if programmed and one ( 1.5 or 2 ) stop bits. the uarts include complete modem control capability and an interrupt system that may be software trailed to the computing time required to handle the communication link. they have fifo mode to reduce the number of interrupts presented to the host. both receiver and transmitter have a
july, 2008 v0.29p 33 F71863 16-byte fifo. the below content is about the uart1 and uart2 device register descriptions. all the registers are for software porting reference. receiver buffer register ? base + 0 bit name r/w default description 7-0 rbr r 00h the data received. read only when lcr[7] is 0 transmitter holding register ? base + 0 bit name r/w default description 7-0 thr w 00h data to be transmitted. write only when lcr[7] is 0 divisor latch (lsb) ? base + 0 bit name r/w default description 7-0 dll r/w 01h baud generator divisor low byte. access only when lcr[7] is 1. divisor latch (msb) ? base + 1 bit name r/w default description 7-0 dlm r/w 00h baud generator divisor high byte. access only when lcr[7] is 1. interrupt enable register ? base + 1 bit name r/w default description 7-4 reserved - - reserved. 3 edssi r/w 0 enable modem status interrupt. access only when lcr[7] is 0. 2 elsi r/w 0 enable line status error in terrupt. access only when lcr[7] is 0. 1 etbfi r/w 0 enable transmitter holding register empty interrupt. access only when lcr[7] is 0. 0 erbfi r/w 0 enable received data available interrupt. access only when lcr[7] is 0. interrupt identification register ? base + 2 bit name r/w default description 7 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 6 fifo_en r 0 0: fifo is disabled 1: fifo is enabled. 5-4 reserved - - reserved.
july, 2008 v0.29p 34 F71863 3-1 irq_id r 000 000: interrupt is caused by modem status 001: interrupt is caused by transmitter holding register empty 010: interrupt is caused by received data available. 110: interrupt is caused by character timeout 011: interrupt is caused by line status. 0 irq_pendn r 1 1: interrupt is not pending. 0: interrupt is pending. fifo control register ? base + 2 bit name r/w default description 7-6 rcv_trig w 00 00: receiver fifo trigger level is 1. 01: receiver fifo trigger level is 4. 10: receiver fifo trigger level is 8. 11: receiver fifo trigger level is 14. 5-3 reserved - - reserved. 2 clrtx r 0 reset the transmitter fifo. 1 clrrx r 0 reset the receiver fifo. 0 fifo_en r 0 0: disable fifo. 1: enable fifo. line control register ? base + 3 bit name r/w default description 7 dlab r/w 0 0: divisor latch can?t be accessed. 1: divisor latch can be accessed via base and base+1. 6 setbrk r/w 0 0: transmitter is in normal condition. 1: transmit a break condition. 5 stkpar r/w 0 4 eps r/w 0 3 pen r/w 0 xx0: parity bit is disable 001: parity bit is odd. 011: parity bit is even 101: parity bit is logic 1 111: parity bit is logic 0 2 stb r/w 0 0: stop bit is one bit 1: when word length is 5 bit stop bit is 1.5 bit else stop bit is 2 bit 1-0 wls r/w 00 00: word length is 5 bit 01: word length is 6 bit 10: word length is 7 bit 11: word length is 8 bit modem control register ? base + 4 bit name r/w default description 7-5 reserved - - reserved. 4 loop r/w 0 0: uart in normal condition. 1: uart is internal loop back 3 out2 r/w 0 0: all interrupt is disabled. 1: interrupt is enabled (disabled) by ier. 2 out1 r/w 0 read from msr[6] is loop back mode 1 rts r/w 0 0: rts# is forced to logic 1 1: rts# is forced to logic 0
july, 2008 v0.29p 35 F71863 0 dtr r/w 0 0: dtr# is forced to logic 1 1: dtr# is forced to logic 0 line status register ? base + 5 bit name r/w default description 7 rcr_err r 0 0: no error in the fifo when fifo is enabled 1: error in the fifo when fifo is enabled. 6 temt r 1 0: transmitter is in transmitting. 1: transmitter is empty. 5 thre r 1 0: transmitter holding register is not empty. 1: transmitter holding register is empty. 4 bi r 0 0: no break condition detected. 1: a break condition is detected. 3 fe r 0 0: data received has no frame error. 1: data received has frame error. 2 pe r 0 0: data received has no parity error. 1: data received has parity error. 1 oe r 0 0: no overrun condition occurred. 1: an overrun condition occurred. 0 dr r 0 0: no data is ready for read. 1: data is received. modem status register ? base + 6 bit name r/w default description 7 dcd r - complement of dcd# input. in loop back mo de, this bit is equivalent to out2 in mcr. 6 ri r - complement of ri# input. in loop back mode , this bit is equivalent to out1 in mcr 5 dsr r - complement of dsr# input. in loop back mode , this bit is equivalent to dtr in mcr 4 cts r - complement of cts# input. in loop back mode , this bit is equivalent to rts in mcr 3 ddcd r 0 0: no state changed at dcd#. 1: state changed at dcd#. 2 teri r 0 0: no trailing edge at ri#. 1: a low to high transition at ri#. 1 ddsr r 0 0: no state changed at dsr#. 1: state changed at dsr#. 0 dcts r 0 0: no state changed at cts#. 1: state changed at cts#. scratch register ? base + 7 bit name r/w default description 7-0 scr r/w 00h scratch register.
july, 2008 v0.29p 36 F71863 7.4 parallel port the parallel port in F71863 supports an ibm xt/at compatible parallel port ( spp ), bi-directional paralle port ( bpp ), enhanced parallel port ( epp ), extended capabilities parallel port ( ecp ) mode. refer to the configuration registers for more information on selecting the mode of operation. the below content is about the parallel port device register descriptions. all the registers are for software porting reference. parallel port data register ? base + 0 bit name r/w default description 7-0 data r/w 00h the output data to dr ive the parallel port data lines. ecp address fifo register ? base + 0 bit name r/w default description 7-0 ecp_afifo r/w 00h access only in ecp parallel port mode and the ecp_mode programmed in the extended control register is 011. the data written to this register is placed in the fifo and tagged as an address/rle. it is auto transmitted by the hardware. the operation is only defined for forward direction. it divide into two parts : bit 7 : 0: bits 6-0 are run length, indicating how many times the next byte to appear (0 = 1time, 1 = 2times, 2 = 3times and so on). 1: bits 6-0 are a ecp address. bit 6-0 : address or rle depends on bit 7. device status register ? base + 1 bit name r/w default description 7 busy_n r - inverted version of parallel port signal busy. 6 ack_n r - version of parallel port signal ack#. 5 perror r - version of parallel port signal pe. 4 select r - version of parallel port signal slct. 3 err_n r - version of parallel port signal err#. 2-1 reserved r 11 reserved. return 11b when read. 0 tmout r - this bit is valid only in epp mode. return 1 when in other modes. it indicates that a 10us time out has occurred on the epp bus. 0: no time out error. 1: time out error occurred, write 1 to clear.
july, 2008 v0.29p 37 F71863 device control register ? base + 2 bit name r/w default description 7-6 reserved - 11 reserved. return 11b when read. 5 dir r/w 0 0: the parallel port is in output mode. 1: the parallel port is in input mode. it is auto reset to 0 when in spp mode. 4 ackirq_en r/w 0 enable an interr upt at the rising edge of ack#. 3 slin r/w 0 inverted and then drives the parallel port signal slin#. when read, the status of inverted slin# is return. 2 init_n r/w 0 drives the parallel port signal init#. when read, the status of init# is return. 1 afd r/w 0 inverted and then drives the parallel port signal afd#. when read, the status of inverted afd# is return. 0 stb r/w 0 inverted and then drives the parallel port signal stb#. when read, the status of inverted stb# is return. epp address register ? base + 3 bit name r/w default description 7-0 epp_addr r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp address write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp address read protocol. epp data register ? base + 4 ? base + 7 bit name r/w default description 7-0 epp_data r/w 00h write this register will cause the hardwar e to auto transmit the written data to the device with the epp data write protocol. read this register will cause the hardwar e to auto receive data from the device by with the epp data read protocol. parallel port data fifo ? base + 400h bit name r/w default description 7-0 c_fifo r/w 00h data written to this fifo is auto transmitted by the hardware to the device by using standard parallel port protocol. it is only valid in ecp and the ecp_mode is 010b.the operation is only for forward direction. ecp data fifo ? base + 400h bit name r/w default description
july, 2008 v0.29p 38 F71863 7-0 ecp_dfifo r/w 00h data written to this fifo when dir is 0 is auto transmitted by the hardware to the device by using ecp parallel port protocol. data is auto read from device into the fifo when dir is 1 by the hardware by using ecp parallel port protocol. read the fifo will return the content to the system. it is only valid in ecp and the ecp_mode is 011b. ecp test fifo ? base + 400h bit name r/w default description 7-0 t_fifo r/w 00h data may be read, written from system to the fifo in any direction. but no hardware handshake occurred on the parallel port lines. it could be used to test the empty, full and threshold of the fifo. it is only valid in ecp and the ecp_mode is 110b. ecp configuration register a ? base + 400h bit name r/w default description 7 irq_mode r 0 0: interrupt is isa pulse. 1: interrupt is isa level. only valid in ecp and ecp_mode is 111b. 6-4 impid r 001 000: the design is 16-bit implementation. 001: the design is 8-bit implementation (default). 010: the design is 32-bit implementation. 011-111: reserved. only valid in ecp and ecp_mode is 111b. 3 reserved - - reserved. 2 bytetran_n r 1 0: when transmitting there is 1 by te waiting in the transceiver that does not affect the fifo full condition. 1: when transmitting the state of the full bit includes the byte being transmitted. only valid in ecp and ecp_mode is 111b. 1-0 reserved r 00 return 00 when read. only valid in ecp and ecp_mode is 111b. ecp configuration register b ? base + 401h bit name r/w default description 7 comp r 0 0: only send uncompressed data. 1: compress data before sending. only valid in ecp and ecp_mode is 111b. 6 reserved r 1 reserved. return 1 when read. only valid in ecp and ecp_mode is 111b.
july, 2008 v0.29p 39 F71863 5-3 ecp_irq_ch r 001 000: the interrupt selected with jumper. 001: select irq 7 (default). 010: select irq 9. 011: select irq 10. 100: select irq 11. 101: select irq 14. 110: select irq 15. 111: select irq 5. only valid in ecp and ecp_mode is 111b. 2-0 ecp_dma_ch r 011 return the dma channel of ecp parallel port. only valid in ecp and ecp_mode is 111b. extended control register ? base + 402h bit name r/w default description 7-5 ecp_mode r/w 000 000: spp mode. 001: ps/2 parallel port mode. 010: parallel port data fifo mode. 011: ecp parallel port mode. 100: epp mode. 101: reserved. 110: test mode. 111: configuration mode. only valid in ecp. 4 errintr_en r/w 0 0: disable the inte rrupt generated on the falling edge of err#. 1: enable the interrupt generated on the falling edge of err#. 3 damen r/w 0 0: disable dma. 1: enable dma. dma starts when serviceintr is 0. 2 serviceintr r/w 1 0: enable the following case of interrupt. dmaen = 1: dma mode. dmaen = 0, dir = 0: set to 1 whenever there are writeintrthreshold or more bytes are free in the fifo. dmaen = 0, dir = 0: set to 1 whenever there are readintrthreshold or more bytes are valid to be read in the fifo. 1 fifofull r 0 0: the fifo has at least 1 free byte. 1: the fifo is completely full. 0 fifoempty r 0 0: the fifo contains at least 1 byte. 1: the fifo is completely empty. 7.5 keyboard contoller the kbc circuit provides the functions included a keyboard and/or a ps/2 mouse, and can be used with ibm ? -compatible personal computers or ps/2-based systems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer.
july, 2008 v0.29p 40 F71863 output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register the status register is an 8-bit read-only register at i/o address 64h, that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command function 20h read command byte
july, 2008 v0.29p 41 F71863 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test returns 055h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bi ts of port1 into status register c2h continuously puts the upper four bi ts of port1 into status register d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh pulse only rc(the reset line) low for 6 s if command byte is even kbc command description
july, 2008 v0.29p 42 F71863 ps2 wakeup function the kbc supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational key (1) ctrl +esc (2) ctrl+f1 (3) ctrl+space (4) any key (5) windows 98 wakeup up key, kbc will assert pme signal. mouse wakeup function has 2 kinds of conditions, when mouse (1) button click or (2) button click and movement, kbc will assert pme signal. those wakeup conditions are controlled by configuration register. 7.6 hardware monitor for the 8-bit adc has the 8mv lsb, the maximum input voltage of the analog pin is 2.048v. therefore the voltage under 2.048v (ex:1.5v) can be directly connected to these analog inputs. the voltage higher than 2.048v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc/vsb/vbat is an exception for it is main power of the F71863. therefore 3vcc/vsb/vbat c an directly connect to this chip?s power pin and need no external resistors. there are two functions in this pin with 3.3v. the first function is to supply internal analog power of the F71863 and the second function is that voltage with 3.3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of +3.3v. there are four voltage inputs in the F71863 and the voltage divided formula is shown as follows: 2 1 2 12 r r r v vin v + = + where v +12v is the analog input voltage, for example. if we choose r1=27k, r2=5.1k, the exact input voltage for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows.
july, 2008 v0.29p 43 F71863 vin (lower than 2.048v) 8-bit adc with 8 mv lsb voltage inputs r1 r2 vin1(max2.048v) vin(higher than 2.048v) (directly connect to the chip) 3vcc/vsb (directly connect to the chip) vin3.3 150k 150k typical thermister connection r thm 10k, 25 c r vref 10k, 1% 2n3906 typical bjt connection d+ d- fig 7-1 the F71863 monitors three remote temperature sensors.these sensors can be measured from -40c to 127c. more detail please refer register description. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906 monitor temperature from ?thermistor? the F71863 can connect three thermistor to measure environment temperature or remote temperature. the specification of thermistor should be considered to (1) value is 3435k (2) resistor value is 10k ohm at 25 c. in the figure 7-1, the thermistor is connected by a serial resistor with 10k ohm, then connected to vref. monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits provide thermal diode for temperature measurement, the F71863 is capable to these situations. the build-in reference table is for pnp 2n3906 transistor. in the figure 7-1, the transistor is directly connected into temperature pins.
july, 2008 v0.29p 44 F71863 adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; therefore, careful pcb board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environmen t. high frequency emi is best filtered at d+ and d- with an external 2200pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sources tested cause the adc measurement to be higher than the actual temperature, depending on the frequency and amplitude. over temperature signal (ovt#) ovt# alert for temperature is shown as figure 7-2. when monitored temperature exceeds the over-temperature threshold value, ovt# will be asserted until the temperature goes below the hysteresis temperature. t hyst to ovt# fig 7-2 temperature pme# pme# interrupt for temperature is shown as figure 7-3. temperature exceeding high limit or going below hysteresis will cause an inte rrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register.
july, 2008 v0.29p 45 F71863 *interrupt reset when interrupt status registers are written 1 smi# to t hyst (pulse mode) (level mode active low) * * * * fig 7-3 fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer outputs are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification. the normal circuit and trimming circuits are shown as follows: fan out +12v gnd pull-up resister 4.7k ohms +12v fan input fanin 1 F71863 22k~30k 10k fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input F71863 > 1k fan with tach pull-up to +12v, or totem-pole putput and zener clamp 3.3v zener fan with tach pull-up to +12v, or totern-pole output and register attenuator fanin 1 fig 7-4 / 7-5
july, 2008 v0.29p 46 F71863 fan out +5v gnd pull-up resister 4.7k ohms +5v fan input fanin1 F71863 1k~2.7k 10k fan connector fan out +5v gnd pull-up resister < 1k or totem-pole output +5v fan input fanin1 F71863 > 1k fan with tach pull-up to +5v, or totem-pole putput and zener clamp 3.3v zener fan with tach pull-up to +5v, or totern-pole output and register attenuator fig 7-6 / 7-7 determine the fan counter according to: r pm count 6 10 5 . 1 = in other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachometer output per round. count rpm 6 10 5 . 1 = fan speed control the F71863 provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle dac fan control the range of dc output is 0~3.3v, controlled by 8-bit register. 1 lsb is about 0.013v. the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 255 value register 8bit programmed 3 . 3 (v) tage output_vol = and the suggested application circuit for linear fan control would be:
july, 2008 v0.29p 47 F71863 dc output voltage r 3.9k r10k 12v pmos r27k 1 2 3 jp1 con3 r 10k d1 1n4148 r 4.7k c 47u fanin monitor c 0.1u 3 2 1 8 4 + - lm358 dc fan control with op fig 7-8 pwm duty fan control the duty cycle of pwm can be programmed by a 8-bit register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g +5v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g fig 7-9 fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode, 3. linear auto mode. more detail, please refer the description of registers. manual mode for manual mode, it generally acts as software fan speed control. stage auto mode at this mode, the F71863 provides automatic fan speed control related to temperature
july, 2008 v0.29p 48 F71863 variation of cpu/gpu or the system. the F71863 can provide two temperature boundaries and three intervals, and each interval has its related fan speed pwm duty. all these values should be set by bios first. take figure 7-10 as example. when temperature boundaries are set as 45 and 75 c and there are three intervals. the related desired fan speed for each interval are 40%, 80% and 100% (fixed) . when the temperature is within 45~75?c, the fan speed will follow 80% pwm duty and that define in registers. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature variation. the F71863 will take charge of all the fan speed control and need no software support. pwm duty 40% 75 degree c 45 degree c temperature 80% 100% temperature fan speed figure 7-10 below is a sample for stage auto mode: set temperature as 60 x c, 40 x c and duty as 100%, 70%, 50% 100% 70% 50% 60 degree c 40 degree c bcd temp. fan speed pwm duty hysteresis 57 degree c a a. once temp. is under 40 x c, the lowest fan speed keeps 50% pwm duty b. once temp. is over 40 x c,60 x c, the fan speed will vary from 70% to 100% pwm duty and increase with temp. level. c. once temp. keeps in 55 x c, fan speed keeps in 70% pwm duty d. if set the hysteresis as 3 x c (default 4 x c), once temp reduces under 57 x c, fan speed reduces to 70% pwm duty and stays there.
july, 2008 v0.29p 49 F71863 linear auto mode otherwise, F71863 supports linear auto mode. below has a example to describe this mode. more detail, please refer the register description. a. linear auto mode (pwm duty i) set temperature as 70 x c, 40 x c and duty as 100%, 70%, 40% 100% 70% 40% 70 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed pwm duty a. once temp. is under 40 x c, the lowest fan speed keeps 40% pwm duty b. once temp. is over 40 x c and under 70 x c, the fan speed will vary from 40% to 70% pwm duty and linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 x c, fan speed will directly increase to 100% pwm duty (full speed) d. if set the hysteresis as 5 x c(default is 4 x c), once temp reduces under 65 x c (not 70 x c), fan speed reduces from 100% pwm duty and decrease linearly with temp.. fan_fault# fan_fault# will be asserted when the fan speed doesn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there are two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan speed count can?t reach the fan expected count in time. (figure 7-11)
july, 2008 v0.29p 50 F71863 fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% fig 7-11 (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count still in 0xfff. 7.7 spi interface communication between the two devices is handling the serial peripheral interface (spi). every spi system consist of one master and one or more slaves, where a master provides the spi clock and slave receives clock from the master. this design is only master function, for basic signal, master-out/slave-in (mosi), master-in/slave-out (miso), serial clock (s ck), and 4 slaves select (ss), are needed for spi interface. each of slave select supports from 512kbits to 4096kbits flash is decided by configuration register. serial clock (sck) signal frequency is varied from 24mhz to 187.5 khz. the serial data (mosi) for spi interface translates to depend on sck rising edge or falling edge is decided by configuration register. 7.8 acpi function the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primary concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect different power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5.
july, 2008 v0.29p 51 F71863 among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v default timing always off vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v always on timing
july, 2008 v0.29p 52 F71863 k8 power sequence timing diagram
july, 2008 v0.29p 53 F71863 st1/st2 pins timing diagram:
july, 2008 v0.29p 54 F71863 pci reset and pwrok signals the F71863 supports 3 output buffers for 3 reset signals. so far as the pwrok issue is as the figure above. pwrok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed by register. (100ms ~ 400ms) 7.9 amdsi and intel peci function the F71863 provides intel peci/amdsi interfaces for new generational cpu temperature sensing. in amdsi interface, there are sic and sid signals for temperature information reading from amd cpu. the sic signal is for clocking use, the other is for data transferring. more detail please refer register description. delay +3.3v atxpg lreset# pcirst1~3# pwrok buffer
july, 2008 v0.29p 55 F71863 sic vddio F71863 amd cpu sic sid 300 300 sid in intel peci interface, the F71863 can connect to cpu directly. the F71863 can read the temperature data from cpu, than the fan control machine of F71863 can implement the fan to cool down cpu temperature. the application circuit is as below. more detail please refer the register description. peci F71863 cpu peci intel 100k avoid pre-bios floating
july, 2008 v0.29p 56 F71863 8. register description the configuration register is used to control the behavior of the co rresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the sout1 pin to change the default value to 0x2e/0x2f. to enable configuration, th e entry key 0x87 must be written to the index port. to disable configuration, write exit key 0xaa to the index port. following is a example to enable configuration and disable conf iguration by using debug. -o 4e 87 -o 4e 87 ( enable configuration ) -o 4e aa ( disable configuration ) the following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their defau lt value. please refer each device chapter if you want more detail information. global control registers ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register - - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 0 0 0 0 0 1 1 0 21 chip id register 0 0 0 0 0 0 0 1 23 vender id register 0 0 0 1 1 0 0 1 24 vender id register 0 0 1 1 0 1 0 0 25 software power down register - - 0 0 0 0 0 0 26 uart irq sharing register 0 - - - - - 0 0 27 rom address select register 0 0/1 1/0 1/0 0/1 0/1 0/1 0 28 power led function select register - - - - 0 0 0 0 29 multi function select 1 register - 0 0 0 - 0 0 0 2a multi function select 2 register 0 0 0 0 0 0 0 0 2b multi function select 3 register 0 0 0 0 0 0 0 0 2c multi function select 4 register 0 0 0 0 0 0 0 0 2d wakeup control register 0 - - - 1 0 0 0
july, 2008 v0.29p 57 F71863 device configuration registers ?-? reserved or tri-state fdc device configuration registers (ldn cr00) register 0x[hex] register name default value msb lsb 30 fdc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 0 0 0 0 70 irq channel select register - - - - 0 1 1 0 74 dma channel select register - - - - - 0 1 0 f0 fdd mode register - - - - 1 1 1 0 f2 fdd drive type register - - - - - - 1 1 f4 fdd selection register - - - 0 0 - 0 0 uart1 device configuration registers (ldn cr01) register 0x[hex] register name default value msb lsb 30 uart1 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 rs485 enable register - - - 0 - - - - uart2 device configuration registers (ldn cr02) register 0x[hex] register name default value msb lsb 30 uart2 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 rs485 enable register - - - 0 0 0 - - f1 sir mode control register - - - 0 0 1 0 0 parallel port device configuration registers (ldn cr03) register 0x[hex] register name default value msb lsb 30 parallel port device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 0 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 1 1 74 dma channel select register - - - 0 - 0 1 1
july, 2008 v0.29p 58 F71863 f0 prt mode select register 0 1 0 0 0 0 1 0 hardware monitor device configuration registers (ldn cr04) register 0x[hex] register name default value msb lsb 30 h/w monitor device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 kbc device configuration registers (ldn cr05) register 0x[hex] register name default value msb lsb 30 kbc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 kb irq channel select register - - - - 0 0 0 0 72 mouse irq channel select register - - - - 0 0 0 0 gpio device configuration registers (ldn cr06) register 0x[hex] register name default value msb lsb f0 gpio output enable register - - - - 0 0 0 0 f1 gpio output data register - - - - 1 1 1 1 f2 gpio pin status register - - - - - - - - f3 gpio drive enable register 0 0 0 0 0 0 0 0 e0 gpio1 output enable register 0 0 0 0 0 0 0 0 e1 gpio1 output data register 1 1 1 1 1 1 1 1 e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register 0 0 0 0 0 0 0 0 d0 gpio2 output enable register 0 0 0 0 0 0 0 0 d1 gpio2 output data register 1 1 1 1 1 1 1 1 d2 gpio2 pin status register - - - - - - - - d3 gpio2 drive enable register 0 0 0 0 0 0 0 0 c0 gpio3 output enable register - - - - 0 0 0 0 c1 gpio3 output data register - - - - 1 1 1 1 c2 gpio3 pin status register - - - - - - - - c3 gpio3 drive enable register - - - - 0 0 0 0 b0 gpio4 output enable register - - 0 0 0 0 0 0 b1 gpio4 output data register - - 1 1 1 1 1 1 b2 gpio4 pin status register - - - - - - - - b3 gpio4 drive enable register - - 0 0 0 0 0 0
july, 2008 v0.29p 59 F71863 vid device configuration registers (ldn cr07) register 0x[hex] register name default value msb lsb 30 vid device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 spi device configuration registers (ldn cr08) register 0x[hex] register name default value msb lsb f0 spi control register 0 0 0 1 0 0 0 0 f1 spi timeout value register 0 0 0 0 0 1 0 0 f2 spi baud rate divisor register - - - - - 0 0 1 f3 spi status register 0 - - - 0 - - - f4 spi high byte data register 0 0 0 0 0 0 0 0 f5 spi command data register 0 0 0 0 0 0 0 0 f6 spi chip select register - - - - 0 0 0 0 f7 spi memory mapping register - - - - - - - - f8 spi operate register 0 0 0 0 0 0 0 0 fa spi low byte data register 0 0 0 0 0 0 0 0 fb spi address high byte register 0 0 0 0 0 0 0 0 fc spi address medium byte register 0 0 0 0 0 0 0 0 fd spi address low byte register 0 0 0 0 0 0 0 0 fe spi program byte register 0 0 0 0 0 0 0 0 ff spi write data register 0 0 0 0 0 0 0 0 pme and acpi device configur ation registers (ldn cr0a) register 0x[hex] register name default value msb lsb 30 pme device enable register - - - - - - - 0 f0 pme event enable register - 0 0 0 0 0 0 0 f1 pme event status register - - - - - - - - f4 acpi control register 0 0 0 0 0 1 1 0 f5 acpi control register 0 0 0 1 1 1 0 0
july, 2008 v0.29p 60 F71863 8.1 global control registers 8.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the regi ster and device powered by vdd ( vcc ). 8.1.2 logic device number register (ldn) ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: select fdc dev ice configuration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: select kbc device c onfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 08h: select spi device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 8.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 06h chip id 1 of F71863fg. 8.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 01h chip id2 of F71863fg. 8.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1 of fintek devices. 8.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 8.1.7 software power down register ? index 25h bit name r/w default description 7-6 reserved - - reserved 5 reserved r/w 0 dummy register.
july, 2008 v0.29p 61 F71863 4 softpd_hm r/w 0 power down the hardware monitor device. this will stop the hardware monitor clock. 3 softpd_prt r/w 0 power down the parallel port device. this will stop the parallel port clock. 2 softpd_ur2 r/w 0 power down the uart 2 device. this will stop the uart 2 clock. 1 softpd_ur1 r/w 0 power down the uart 1 device. this will stop the uart 1 clock. 0 softpd_fdc r/w 0 power down the fdc device. this will stop the fdc clock. 8.1.8 uart irq sharing register ? index 26h bit name r/w default description 7 clk24m_sel r/w 0 0: clkin is 48mhz 1: clkin is 24mhz 6-2 reserved - - reserved. 1 irq_mode r/w 0 0: pci irq sharing mode (low level). 1: isa irq sharing mode (low pulse). o irq_shar r/w 0 0: disable irq sharing of two uart devices. 1: enable irq sharing of two uart devices. 8.1.9 rom address select register ? index 27h bit name r/w default description 7 rom_wr_en r/w 0 0: disable rom writing 1: enable rom writing 6 spi_en r/w - 0: spi disable 1: spi enable this register is power on trapped by sout2/spi_trap. pull down to enable spi. 5 spi_bios_en r/w - 0: use spi bridge for bios 1: reserved this register is power on trapped by dtr2#/fwh_trap. pull down to enable spi bridge for bios. 4 port_4e_en r/w - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by so ut1/ config4e_2e. pull down to select port 2e/2f. 3 seg_000e_en r/w - 0: disable address 0x000e0000 ? 0x000effff decode 1: enable address 0x00 0e0000 ? 0x000effff decode this register is power on trapped by sout2/spi_dis. pull down to enable. 2 seg_fff8_en r/w - 0: disable address 0xfff80000 ? 0xffffffff and 0x000f0000 ? 0x000fffff decode 1: enable address 0xfff80000 ? 0xffffffff and 0x000f0000 ? 0x000fffff decode this register is power on trapped by sout2/spi_dis. pull down to enable.
july, 2008 v0.29p 62 F71863 1 seg_ffef_en r/w - 0: disable address 0xffee ? 0xffefffff decode 1: enable address 0xffee0000 ? 0xffefffff decode this register is power on trapped by sout2/spi_dis. pull down to enable. 0 seg_fff0_en r/w 0 0: disable address 0xfff00000 ? 0xfff7ffff decode 1: enable address 0xfff00000 ? 0xfff7ffff decode 8.1.10 power led function select register ? index 28h bit name r/w default description 7-4 reserved - - reserved. 3 gpio43_sel r/w 0 0: irrx/gpio43 functions as irrx. 1: irrx/gpio43 functions as gpio43. 2 gpio42_sel r/w 0 0: irtx/gpio42 functions as irtx. 1: irtx/gpio42 functions as gpio42. 1 gpio41_sel r/w 0 0: fanctrl3/gpio41 functions as fanctrl3. 1: fanctrl3/gpio41 functions as gpio41. 0 gpio40_sel r/w 0 0: fanin3/gpio40 functions as fanin3. 1: fanin3/gpio40 functions as gpio40. 8.1.11 multi function select 1 register ? index 29h (powered by vsb3v) bit name r/w default description 7 reserved r/w - reserved 6 fdd_prot_sts r/w 0 0: fdd write-protect stat us depends on pin18(wpt#) 1: fdd is write-protected 5 lec_vcc_pro r/w 0 0: led_vcc (pin65) is tri-state if vcc power loss 1: led_vcc (pin65) is still programmable while vcc power loss 4 kb_mo_swp r/w 0 0: kb/mouse signal as default. 1: kb/mouse signal swapped. 3 reserved r/w - reserved 2 gpio02_sel r/w 0 0: slotocc#/gpio02 will functions as slotocc#. 1: slotocc#/gpio02 will functions as gpio02. 1 wdt_gp03_en r/w 0 0: gpio03/wdtrst# will function as gpio03 1: gpio03/wdtrst# will function as wdtrst#. 0 alert_gp_en r/w 0 0: gpio15/led_vsb/alert# will func tion as gpio15/led_vsb controlled by gpio15_sel register. 1: gpio15/led_vsb/alert# will function as alert#. 8.1.12 multi function select 2 register ? index 2ah (powered by vsb3v) bit name r/w default description
july, 2008 v0.29p 63 F71863 7-6 vsbled_sel r/w 2?b00 vsbled function select, powered by vsb. 00: vsbled always output low. 01: vsbled tri-state 10: vsbled output 0.5hz clock. 11: vsbled output 1hz clock. ( clock output is inverse with vddled clock output ) 5-4 vddled_sel r/w 2?b00 vddled function select, powered by vdd. 00: vddled always output low. 01: vddled tri-state 10: vddled output 0.5hz clock. 11: vddled output 1hz clock. ( clock output is inverse with vsbled clock output ) 3 gpio33_sel r/w 0 0: rsmrst#/gpio33 functions as rsmrst#. 1: rsmrst#/gpio33 functions as gpio33. 2 gpio32_sel r/w 0 0: pwrok/gpio32 functions as pwrok. 1: pwrok/gpio32 functions as gpio32. 1 gpio31_sel r/w 0 0: ps_on#/gpio31 functions as ps_on#. 1: ps_on#/gpio31 functions as gpio31. 0 gpio30_sel r/w 0 0: s3#/gpio30 functions as s3#. 1: s3#/gpio30 functions as gpio30. 8.1.13 multi function select 3 register ? index 2bh (powered by vsb3v) bit name r/w default description 7 reserved r/w 0 dummy register. 6 gpio16_sel r/w 0 0: gpio16/led_vcc functions as gpio16. 1: gpio16/led_vcc functions as led_vcc. 5 gpio15_sel r/w 0 when register alert_gp_en is 0, the register functions as: 0: gpio15/led_vsb/alert# functions as gpio15. 1: gpio15/led_vsb/alert# functions as led_vsb. 4 gpio14_sel r/w 0 0: gpio14/fwh_dis/wdtrst# functions as gpio14 when spi is disabled. 1: gpio14/fwh_dis/wdtrst# func tions as wdtrst# when spi is disabled. 3 gpio13_sel r/w 0 0: gpio13/spi_mosi/beep functions as gpio13 when spi is disabled. 1: gpio13/spi_mosi/beep functions as beep when spi is disabled. 2 gpio12_sel r/w 0 0: gpio12/spi_miso/fanctrl1_1 func tions as gpio12 when spi is disabled. 1: gpio12/spi_niso/fanctrl1_1 functions as fanctrl1_1 when spi is disabled. 1-0 reserved r/w 0 reserved 8.1.14 multi function select 4 register ? index 2ch (powered by vsb3v) bit name r/w default description
july, 2008 v0.29p 64 F71863 7 gpio27_sel r/w 0 0: pwsout#/gpio27 functions as pwsout#. 1: pwsout#/gpio27 functions as gpio27. 6 gpio26_sel r/w 0 0: pwsin#/gpio26 functions as pwsin#. 1: pwsin#/gpio26 functions as gpio26. 5 gpio25_sel r/w 0 0: pme#/gpio25 functions as pme#. 1: pme#/gpio25 functions as gpio25. 4 gpio24_sel r/w 0 0: atxpg_in/gpio24 functions as atxpg_in. 1: atxpg_in/gpio24 functions as gpio24. 3 reserved r/w 0 reserved 2 gpio22_sel r/w 0 0: pcirst3#/gpio22 functions as pcirst3#. 1: pcirst3#/gpio22 functions as gpio22. 1 gpio21_sel r/w 0 0: pcirst2#/gpio21 functions as pcirst2#. 1: pcirst2#/gpio21 functions as gpio21. 0 gpio20_sel r/w 0 0: pcirst1#/gpio20 functions as pcirst1#. 1: pcirst1#/gpio20 functions as gpio20. 8.1.15 wakeup control register ? index 2dh (powered by vbat) bit name r/w default description 7 spi_cs1_en r/w 0 this register decides the architecture of spi when used as primary bios. 1: use two 4mbits. (fwh_dis will multi-functions as spi_cs1#) 0: use one 8mbits. (divided into two 4mbi ts. originally use the higher part. if the higher part is booting fail, the memory address will be auto mapped to lower part.) 6-4 reserved r/w 0 dummy register. 3 wakeup_en r/w 1 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. 2-1 key_sel r/w 00 this registers select the keyboard wake up key. when key_sel_add is low, the register indicates 00: wake up key is ctrl + esc. 01: wake up key is ctrl + f1. 10: wake up key is ctrl + space. 11: wake up key is any key. otherwise, wake up key is win98 wakeup key. 0 mo_sel r/w 0 this register selects the mouse wake up key. 0: wake up by click. 1: wake up by click and movement.
july, 2008 v0.29p 65 F71863 8.2 fdc registers (cr00) 8.2.1 fdc configuration registers fdc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 fdc_en r/w 1 0: disable fdc. 1: enable fdc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of fdc base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f0h the lsb of fdc base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selfdcirq r/w 06h select the irq channel for fdc. dma channel select register ? index 74h bit name r/w default description 7-3 reserved - - reserved. 2-0 selfdcdma r/w 010 select the dma channel for fdc. fdd mode register ? index f0h bit name r/w default description 7-4 reserved - - reserved. 3-2 if_mode r/w 11 00: model 30 mode. 01: ps/2 mode. 10: reserved. 11: at mode (default). 1 fdmamode r/w 1 0: enable burst mode. 1: non-busrt mode (default). 0 en3mode r/w 0 0: normal floppy mode (default). 1: enhanced 3-mode fdd. fdd drive type register ? index f2h bit name r/w default description 7-2 reserved - - reserved.
july, 2008 v0.29p 66 F71863 1-0 fdd_type r/w 11 fdd drive type. fdd selection register ? index f4h bit name r/w default description 7-5 reserved - - reserved. 4-3 fdd_drt r/w 00 data rate table select, refer to table a. 00: select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 mega tape. 11: reserved. 2 reserved - - reserved. 1-0 fdd_dt r/w 00 drive type select, refer to table b. table a data rate table select data ra te selected data rate densel fdd_drt[1] fdd_drt[0] datarate1 datarate0 mfm fm 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 0 0 1 1 1meg --- 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 0 1 1 1 1meg --- 1 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 1 0 1 1 1meg --- 1 table b drive type fdd_dt1 fdd_dt0 drvden0 remark 0 0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? 1/1.6/1 mb 3.5? (3-mode ) 0 1 datarate1 1 0 densel# 1 1 datarate0
july, 2008 v0.29p 67 F71863 8.3 uart1 registers (cr01) 8.3.1 uart 1 configuration registers uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur1_en r/w 1 0: disable uart 1. 1: enable uart 1. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 1 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 1 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur1irq r/w 4h select t he irq channel for uart 1. rs485 enable register ? index f0h bit name r/w default description 7-5 reserved - - reserved. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# low when transmitting data. 3-0 reserved - - reserved.
july, 2008 v0.29p 68 F71863 8.4 uart 2 registers (cr02) 8.4.1 uart 2 configuration registers uart 2 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur2_en r/w 1 0: disable uart 2. 1: enable uart 2. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of uart 2 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 2 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur2irq r/w 3h select t he irq channel for uart 2. rs485 enable register ? index f0h bit name r/w default description 7-5 reserved - - reserved. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# low when transmitting data. 3 rxw4c_ir r/w 0 0: no reception delay when sir is changed form tx to rx. 1: reception delays 4 characters time when sir is changed form tx to rx. 2 txw4c_ir r/w 0 0: no transmission delay when sir is changed form rx to tx. 1: transmission delays 4 characters time when sir is changed form rx to tx. 1-0 reserved - - reserved. sir mode control register ? index f1h bit name r/w default description 7 reserved - - reserved. 6 reserved - - reserved. 5 reserved - - reserved. 4-3 irmode r/w 00 00: disable ir function. 01: disable ir function. 10: irda function, active pulse is 1.6us. 11: irda function, active pulse is 3/16 bit time.
july, 2008 v0.29p 69 F71863 2 hduplx r/w 1 0: sir is in full duplex mode for loopbak test. txw4c_ir and rxw4c_ir are of no use. 1: sir is in half duplex mode. 1 txinv_ir r/w 0 0: irtx is in normal condition. 1: inverse the irtx. 0 rxinv_ir r/w 0 0: irrx is in normal condition. 1: inverse the irrx.
july, 2008 v0.29p 70 F71863 8.5 parallel port registers (cr03) 8.5.1 parallel port configuration registers parallel port device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 prt_en r/w 1 0: disable parallel port. 1: enable parallel port. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of parallel port base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 78h the lsb of parallel port base address. irq channel select register ? index 70h bit name r/w default description 7-5 reserved - - reserved. 3-0 selprtirq r/w 7h select the irq channel for parallel port. dma channel select register ? index 74h bit name r/w default description 7-5 reserved - - reserved. 4 ecp_dma_mode r/w 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - reserved. 2-0 selprtdma r/w 011 select the dma channel for parallel port. prt mode select register ? index f0h bit name r/w default description 7 spp_irq_mode r/w 0 interrupt mode in non-ecp mode. 0: level mode. 1: pulse mode. 6-3 ecp_fifo_thr r/w 1000 ecp fifo threshold.
july, 2008 v0.29p 71 F71863 2-0 prt_mode r/w 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode.
july, 2008 v0.29p 72 F71863 8.6 hardware monito r registers (cr04) 8.6.1 hardware monitor configuration registers hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hardware monitor base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the irq channel for hardware monitor. 8.6.2 device registers before the device registers, the following is a register map order which shows a summary of all registers. please refer each one register if you want more detail information. register cr01 ~ cr03 ? configuration registers register cr10 ~ cr4f ? voltage setting register register cr60 ~ cr8e ? temperature setting register register cr90 ~ crdf ? fan control setting register ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf ? fan3 detail setting crc0 ~ crcf 8.6.2.1 configuration register ? index 01h bit name r/w default description 7-3 reserved 0h 0 reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monito ring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode.
july, 2008 v0.29p 73 F71863 8.6.2.2 configuration register ? index 02h bit name r/w default description 7 reserved r/w 0 dummy register. 6 case_beep_en r/w 0 0: disable case open event output via beep. 1: enable case open event output via beep. 5-4 ovt_mode r/w 0 00: the ovt# will be low active level mode. 01: the ovt# will be high active level mode. 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 reserved r/w 0 dummy register. 2 case_smi_en r / w 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. 8.6.2.3 configuration register ? index 03h bit name r/w default description 7-1 reserved r/w 0 return 0 when read. 0 case_sts r/w 0 case open event status, wr ite 1 to clear if case open event cleared. 8.6.2.4 configuration register ? index 0ah bit name r/w default description 7-6 reserved - 00 reserved. 5 t1_iir_en r/w 0 set 1 to enable iir for amdsi/peci reading. the reading will be more stable. 4 reserved r/w 0 reserved. 3-2 vtt_sel r/w 0 peci (vtt) voltage select. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v 1-0 meas_type r/w 00 cpu temperature m easurement method. 00: with external diode. 01: with peci interface. 10: with amdsi interface. 11: reserved. 8.6.2.5 configuration register ? index 0bh (meas_type == 2?b01) bit name r/w default description 7-4 cpu_sel r/w 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping() command to find cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 0, i.e. peci address is 0x31. 0100: cpu is in socket 0, i.e. peci address is 0x32. 1000: cpu is in socket 0, i.e. peci address is 0x33. otherwise are reserved. 3-1 reserved - 0 reserved.
july, 2008 v0.29p 74 F71863 0 domain1_en r/w 0 if the cpu selected is dual core. set this register 1 to read the temperature of domain1. 8.6.2.6 configuration register ? index 0bh (meas_type ==2?b10) bit name r/w default description 7-0 amdsi_ver r - return the amdsi version. 8.6.2.7 configuration register ? index 0ch (meas_type == 2?b01) bit name r/w default description 7-0 tcc_temp r/w 8?h55 tcc activation temperature. the absolute value of cpu temperatur e is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is 0 ~ 255. 8.6.2.8 configuration register ? index 0ch (meas_type ==2?b10) bit name r/w default description 7-0 node_id r - return the amdsi node id. 8.6.2.9 configuration register ? index 0dh bit name r/w default description 7-0 reserved - - reserved. 8.6.2.10 configuration register ? index 0eh bit name r/w default description 7-4 reserved r/w 0 reserved. 3 peci_scale_add r / w 0 this register is used to indicate ho w to calculate the peci reading with peci_scale register. 0: the real value is the readi ng adds the value calculated by peci_scale. 1: the real value is the readi ng adds the value calculated by peci_scale. 2 - 0 peci_scale r / w 0 this register is used to control the peci reading slope. see also peci_scale_add register. 000: the real value is the peci reading. 001: the real value is (1 1/2) peci reading. 010: the real value is (1 1/4) peci reading. 011: the real value is (1 1/8) peci reading. 100: the real value is (1 1/16) peci reading. 101: the real value is (1 1/32) peci reading. 110: the real value is (1 1/64) peci reading. 111: the real value is (1 1/128) peci reading. 8.6.2.11 configuration register ? index 0fh bit name r/w default description 7-0 reserved. - - reserved
july, 2008 v0.29p 75 F71863 voltage setting 8.6.2.12 voltage1 voltage reading and limit ? index 20h- 4fh address attribute default value description 20h ro -- vcc3v reading. the unit of reading is 8mv. 21h ro -- v1 (vcore) reading. the unit of reading is 8mv. 22h ro -- v2 reading. the unit of reading is 8mv. 23h ro -- v3 reading. the unit of reading is 8mv. 24h ro -- v4 reading. the unit of reading is 8mv. 25h ro -- v5 reading. the unit of reading is 8mv. 26h ro -- v6 reading. the unit of reading is 8mv. 27h ro -- vsb3v reading. the unit of reading is 8mv. 28h ro -- vbat reading. the unit of reading is 8mv. 29~2fh ro ff reserved 30~4fh ro ff reserved temperature setting 8.6.2.13 temperature pme# enable register ? index 60h bit name r/w default description 7 en_ t3_ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds ovt setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds high limit setting. 2 en_ t2_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved 8.6.2.14 temperature interrupt status register ? index 61h bit name r/w default description 7 t3_ovt_sts r/w 0 a one indicates temp3 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 6 t2_ovt _sts r/w 0 a one indicates temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 5 t1_ovt _sts r/w 0 a one indicates temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 4 reserved r/w 0 reserved 3 t3_exc _sts r/w 0 a one indicates temp3 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored.
july, 2008 v0.29p 76 F71863 2 t2_exc _sts r/w 0 a one indicates temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 1 t1_exc _sts r/w 0 a one indicates temp1 temperature s ensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved r/w 0 reserved 8.6.2.15 temperature real time status register ? index 62h bit name r/w default description 7 t3_ovt r/w 0 set when the temp3 exceeds the ovt limit. clear when the temp3 is below the ?ovt limit ?hysteresis? temperature. 6 t2_ovt r/w 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 reserved r/w 0 reserved 3 t3_exc r/w 0 set when the temp3 exceeds the high limit. clear when the temp3 is below the ?high limit ?hysteresis? temperature. 2 t2_exc r/w 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 reserved r/w 0 reserved 8.6.2.16 temperature beep enable register ? index 63h bit name r/w default description 7 en_ t3_ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp3 exceeds high limit setting. 2 en_ t2_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved 8.6.2.17 ovt output enable register 1 ? index 66h bit name r/w default description 7 en_t3_alert r 0 enable temperature 3 alert event (a sserted when temperature over high limit) 6 en_t2_alert r 0 enable temperature 2 alert event (a sserted when temperature over high limit) 5 en_t1_alert r 0 enable temperature 1 alert event (a sserted when temperature over high limit) 4 reserved r 0 reserved for temp4
july, 2008 v0.29p 77 F71863 3 en_t3_ovt r/w 0 enable over temperature (ovt ) mechanism of temperature3. 2 en_t2_ovt r/w 0 enable over temperature (ovt ) mechanism of temperature2. 1 en_t1_ovt r/w 1 enable over temperature (ovt ) mechanism of temperature1. 0 reserved r 0h reserved. 8.6.2.18 temperature sensor type register ? index 6bh bit name r/w default description 7-4 reserved ro 0 -- 3 t3_mode r/w 1 0: temp3 is connected to a thermistor 1: temp3 is connected to a bjt.(default) 2 t2_mode r/w 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved r 0h -- 8.6.2.19 temp1 limit hystersis select register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 3-0 reserved r 0h -- 8.6.2.20 temp2 and temp3 limit hyst ersis select register -- index 6dh bit name r/w default description 7-4 temp3_hys r/w 2h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 3-0 temp2_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 8.6.2.21 diode open status register -- index 6fh bit name r/w default description 7-4 reserved ro 0h reserved 3 t3_diode_open ro 0h external diode 3 is open 2 t2_diode_open ro 0h external diode 2 is open 1 t1_diode_open ro 0h this register indicate s the abnormality of temperature 1 measurement. when amdsi interface is enabled, it indicates the error of not receiving ack bit when read tcon command is asserted. when peci interface is enabled, it indicates a error code is received from peci slave. when external diode is used, it indicates the bjt is open or short. 0 reserved r 0h -- temperature ? index 70h- 8fh address attribute default value description 70h reserved ffh reserved
july, 2008 v0.29p 78 F71863 71h reserved ffh reserved 72h ro -- temperature 1 reading. the unit of reading is 1 o c.at the moment of reading this register. 73h ro -- reserved 74h ro -- temperature 2 reading. the unit of reading is 1 o c.at the moment of reading this register. 75h ro -- reserved 76h ro -- temperature 3 reading. the unit of reading is 1 o c.at the moment of reading this register. 77-7bh ro -- reserved 7c-7fh ro ffh reserved 80h reserved ffh reserved 81h reserved ffh reserved 82h r/w 64h temperature sensor 1 ovt limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 high limit. the unit is 1 o c. 86h r/w 55h temperature sensor 3 ovt limit. the unit is 1 o c. 87h r/w 46h temperature sensor 3 high limit. the unit is 1 o c. 88-8bh ro -- reserved 8c~8dh ro ffh reserved 8.6.2.22 temperature filter select register -- index 8eh bit name r/w default description 7-6 iir-queur3 r/w 0h the queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. 5-4 iir-queur2 r/w 0h the queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. 3-2 iir-queur1 r/w 0h the queue time for second filter to quickly update values. 00: disable. 01: 16 times. 10: 32 times. (default) 11: 48 times. 0 reserved r 0h -- fan control setting 8.6.2.23 fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved ro 0h reserved 2 en_fan3_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt.. set this bit 1 to enable pme# function for fan3. 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2.
july, 2008 v0.29p 79 F71863 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. 8.6.2.24 fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved ro 0 reserved 2 fan3_sts r/w -- this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 8.6.2.25 fan real time status register ? index 92h bit name r/w default description 7-3 reserved -- 0 reserved 2 fan3_exc ro -- this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 1 fan2_exc ro -- this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 0 fan1_exc ro -- this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or when duty not ze ro but fan stop over then 3 sec. 8.6.2.26 fan beep# enable register ? index 93h bit name r/w default description 7 full_with_t3_en r/w 0 set one will enable fan to force full speed when t3 over high limit. 6 full_with_t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4 reserved r/w 0 reserved for local temperature. 3 reserved r 0 reserved. 2 en_fan3_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 1 en_fan2_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 0 en_fan1_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 8.6.2.27 fan type select register -- index 94h bit name r/w default description 7-6 reserved r 0 reserved. 5-4 fan3_type r/w 2?b 0s 00: output pwm mode (pushpull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal . 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. 3-2 fan2_type r/w 2?b 0s 00: output pwm mode (pushpull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal . 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved.
july, 2008 v0.29p 80 F71863 1-0 fan1_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal . 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. s : register default values are decided by trapping. 8.6.2.28 fan mode select register -- index 96h bit name r/w default description 7-6 reserved r 0 reserved. 5-4 fan3_mode r/w 1h 00: reserved 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle (voltage) that define in 0xb6-0xbe. 10: reserved 11: manual mode fan control, user can write expect duty cycle (pwm fan type) or voltage(linear fan type) to 0xc3, and f71883fg will output this value duty or voltage to control fan speed. 3-2 fan2_mode r/w 1h 00: reserved. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle (voltage) that define in 0xb6-0xbe. 10: reserved. 11: manual mode fan control, user can write expect duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and f71883fg will output this value duty or voltage to control fan speed. 1-0 fan1_mode r/w 1h 00: reserved. 01: auto fan speed control, fan spee d will follow different temperature by different duty cycle that define in 0xa6-0xae. 10: reserved. 11: manual mode fan control, user can write expect duty cycle (pwm fan type) or voltage(linear fan type) to 0xa3, and f71883fg will output this value duty or voltage to control fan speed. 8.6.2.29 auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 3-0 fan1_hys r/w 4h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 8.6.2.30 auto fan3 and fan4 boundary hystersis select register -- index 99h bit name r/w default description 7-4 reserved r 0 reserved. 3-0 fan3_hys r/w 2h 0000: boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 8.6.2.31 auto fan3 and fan4 boundary hystersis select register -- index 9bh bit name r/w default description 7-6 reserved r 0 reserved.
july, 2008 v0.29p 81 F71863 5-4 fan3_rate_sel r/w 1h fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_rate_sel r/w 1h fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_rate_sel r/w 1h fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 8.6.2.32 fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_stop_duty r/w 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop_duty r/w 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 8.6.2.33 fan3 start up duty-cycle/voltage ? index 9dh bit name r/w default description 7-4 reserved r 0 reserved. 3-0 fan3_stop_duty r/w 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 8.6.2.34 fan fault time register -- index 9fh bit name r/w default description 7-5 reserved -- -- reservd 4 full_duty_sel r/w -- 0: the full duty is 100%. 1: the full duty is 60% (default). this register is power on trap by dtr1#. 3-0 reserved r 0 reserved. fan1 index a0h- afh address attribute default value description
july, 2008 v0.29p 82 F71863 a0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h - - reserved a3h r/w 8?h01 the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). 8.6.2.35 vt1 boundary 1 temperature ? index a6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1tmp1 r/w 3ch (60 o c) the 1 st boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load full speed duty 8?hff. when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 1 register (index abh). 8.6.2.36 vt1 boundary 2 temperature ? index a9 bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound4tmp1 r/w 1eh (30 o c) the 2 st boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index abh). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 2 register (index aeh). 8.6.2.37 fan1 segment 1 speed count ? index abh bit name r/w default description 7 - 0 sec1speed1 r / w d9h (85%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.38 fan1 segment 2 speed count ? index aeh bit name r/w default description 7 - 0 sec2speed1 r / w 80h (50%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.39 fan1 temperature ma pping select ? index afh bit name r/w default description 7-6 reserved -- 0 reserved 5 fan1_up_t_en r / w 0 set 1 to force fan1 to full speed if any temperature over its high limit.
july, 2008 v0.29p 83 F71863 4 fan1_interpolation_ en r/w 0 set 1 will enable the interpolati on of the fan expect table. 3 fan1_jump_high_en r / w 1 this register controls the fan1 dut y movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_rate_sel register (index 9bh). 1: the fan1 duty will directly jumps to full speed. 2 fan1_jump_low_en r / w 1 this register controls the fan1 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_rate_sel register (index 9bh). 1: the fan1 duty will directly jumps to the value of sec1speed1 register. 1-0 fan1_temp_sel r/w 1h 0: reserved. 1: fan1 follow temperature 1. 2: fan1 follow temperature 2. 3: fan1 follow temperature 3. fan2 index b0h- bfh address attribute default value description b0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan1 count reading (lsb). b2h r/w 8?h00 reserved b3h r/w 8?h01 the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan1 full speed count reading (lsb). 8.6.2.40 vt2 boundary 1 temperature ? index b6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1tmp2 r/w 3ch (60 o c) the 1 st boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expect value will load full speed duty 8?hff. when vt2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 1 register (index bbh). 8.6.2.41 vt2 boundary 2 temperature ? index b9 bit name r/w default description 7 reserved ro 0 return 0 when read.
july, 2008 v0.29p 84 F71863 6-0 bound2tmp1 r/w 1eh (30 o c) the 2 st boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index bbh). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 2 register (index beh). 8.6.2.42 fan2 segment 1 speed count ? index bbh bit name r/w default description 7 - 0 sec1speed2 r / w d9h (85%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.43 fan2 segment 2 speed count ? index beh bit name r/w default description 7 - 0 sec2speed2 r / w 80h (50%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.44 fan2 temperature ma pping select ? index bfh bit name r/w default description 7-6 reserved -- 0 reserved 5 fan2_up_t_en r / w 0 set 1 to force fan2 to full speed if any temperature over its high limit. 4 fan2_interpolation_ en r/w 0 set 1 will enable the interpolat ion of the fan expect table. 3 fan2_jump_high_en r / w 1 this register controls the fan2 dut y movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_rate_sel register (index 9bh). 1: the fan2 duty will directly jumps to full speed. 2 fan2_jump_low_en r / w 1 this register controls the fan2 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_rate_sel register (index 9bh). 1: the fan2 duty will directly jumps to the value of sec1speed2 register. 1-0 fan2_temp_sel r/w 2h 0: reserved. 1: fan2 follow temperature 1. 2: fan2 follow temperature 2. 3: fan2 follow temperature 3. fan3 index c0h- cfh address attribute default value description c0h ro 8?h0f fan3 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h - - reserved.
july, 2008 v0.29p 85 F71863 c3h r/w 8?h01 the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prev ent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 8?hff fan3 full speed count reading (lsb). 8.6.2.45 vt3 boundary 1 temperature ? index c6h bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound1tmp3 r/w 3ch (60 o c) the 1 st boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expect value will load the full speed duty 8?hff. when vt3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 1 register (index cbh). 8.6.2.46 vt3 boundary 2 temperature ? index c9 bit name r/w default description 7 reserved ro 0 return 0 when read. 6-0 bound2tmp3 r/w 1eh (30 o c) the 2 st boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expect value will load from segment 1 register (index cbh). when vt3 temperature is below this boundary ? hysteresis, fan3 expect value will load from segment 2 register (index ceh). 8.6.2.47 fan3 segment 1 speed count ? index cbh bit name r/w default description 7 - 0 sec1speed3 r / w d9h (85%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.48 fan3 segment 2 speed count ? index ceh bit name r/w default description 7 - 0 sec2speed3 r / w 80h (50%) the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.6.2.49 fan3 temperature ma pping select ? index cfh bit name r/w default description 7-6 reserved -- 0 reserved 5 fan3_up_t_en r / w 0 set 1 to force fan3 to full speed if any temperature over its high limit. 4 fan3_interpolation_ en r/w 0 set 1 will enable the interpolat ion of the fan expect table. 3 fan3_jump_high_en r / w 1 this register controls the fan3 dut y movement when temperature over highest boundary. 0: the fan3 duty will increases with the slope selected by fan3_rate_sel register (index 9bh). 1: the fan3 duty will directly jumps to full speed.
july, 2008 v0.29p 86 F71863 2 fan3_jump_low_en r / w 1 this register controls the fan3 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan3 duty will decreases with the slope selected by fan3_rate_sel register (index 9bh). 1: the fan3 duty will directly jumps to the value of sec1speed3 register. 1-0 fan3_temp_sel r/w 3h 0: reserved. 1: fan3 follow temperature 1. 2: fan3 follow temperature 2. 3: fan3 follow temperature 3.
july, 2008 v0.29p 87 F71863 8.7 kbc registers (cr05) 8.7.1 kbc configuration registers kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc command port address. the address of data port is command port address + 4; base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc command port address. the address of data port is command port address + 4. kb irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selkirq r/w 0h select the irq channel for keyboard interrupt. mouse irq channel select register ? index 72h bit name r/w default description 7-4 reserved - - reserved. 3-0 selmirq r/w 0h select the irq channel for ps/2 mouse interrupt.
july, 2008 v0.29p 88 F71863 8.8 gpio registers (cr06) 8.8.1 gpio0 registers gpio0 output enable register ? index f0h bit name r/w default description 7-4 reserved - 0 reserved 3 gpio03_oe r/w 0 0: gpio03 is in input mode. 1: gpio03 is in output mode. 2 gpio02_oe r/w 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. 1 reserved r/w 0 reserved 0 reserved r/w 0 reserved gpio0 output data register ? index f1h bit name r/w default description 7-4 reserved - 0 reserved 3 gpio03_val r/w 1 0: gpio03 out puts 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 1 0: gpio02 out puts 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 reserved r/w 1 reserved 0 reserved r/w 1 reserved gpio0 pin status register ? index f2h bit name r/w default description 7-4 reserved - 0 reserved 3 gpio03_in r - the pin stat us of gpio03/wdtrst#. 2 gpio02_in r - the pin stat us of slotocc#/gpio02. 1 reserved r - reserved 0 reserved r - reserved gpio0 drive enable register ? index f3h bit name r/w default description 7-4 reserved - 0 reserved 3 gpio03_drv_en r/w 0 0: gpio03 is open drain in output mode. 1: gpio03 is push pull in output mode. 2 gpio02_drv_en r/w 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode. 1 reserved r/w 0 reserved 0 reserved r/w 0 reserved
july, 2008 v0.29p 89 F71863 8.8.2 gpio1 registers gpio1 output enable register ? index e0h bit name r/w default description 7 reserved r/w 0 reserved 6 gpio16_oe r/w 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? index e1h bit name r/w default description 7 reserved r/w 1 reserved 6 gpio16_val r/w 1 0: gpio16 out puts 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 1 0: gpio15 out puts 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 1 0: gpio14 out puts 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 out puts 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 out puts 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 out puts 0 when in output mode. 1: gpio10 outputs 1 when in output mode. gpio1 pin status register ? index e2h bit name r/w default description 7 reserved r - reserved 6 gpio16_in r - the pin st atus of gpio16/led_vcc 5 gpio15_in r - the pin status of gpio15/led_vsb/alert#. 4 gpio14_in r - the pin status of gpio14/fwh_dis/wdtrst#/spi_cs1#. 3 gpio13_in r - the pin stat us of gpio13/spi_mosi/beep.
july, 2008 v0.29p 90 F71863 2 gpio12_in r - the pin status of gpio12/spi_miso/fanctrl1_1. 1 gpio11_in r - the pin status of gpio11/spi_cs. 0 gpio10_in r - the pin st atus of gpio10/spi_clk. gpio1 drive enable register ? index e3h bit name r/w default description 7 reserved r/w 0 reserved 6 gpio16_drv_en r/w 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. 8.8.3 gpio2 registers gpio2 output enable register ? index d0h bit name r/w default description 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio26 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 reserved r/w 0 reserved 2 gpio22_oe r/w 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. gpio2 output data register ? index d1h bit name r/w default description
july, 2008 v0.29p 91 F71863 7 gpio27_val r/w 1 0: gpio27 out puts 0 when in output mode. 1: gpio27 outputs1 when in output mode. 6 gpio26_val r/w 1 0: gpio26 out puts 0 when in output mode. 1: gpio26 outputs1 when in output mode. 5 gpio25_val r/w 1 0: gpio25 out puts 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 1 0: gpio24 out puts 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 reserved r/w 1 reserved 2 gpio22_val r/w 1 0: gpio22 out puts 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 1 0: gpio21 out puts 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 1 0: gpio20 out puts 0 when in output mode. 1: gpio20 outputs 1 when in output mode. gpio2 pin status register ? index d2h bit name r/w default description 7 gpio27_in r - the pin stat us of pwsout#/gpio27. 6 gpio26_in r - the pin st atus of pwsin#/gpio26. 5 gpio25_in r - the pin status of pme#/gpio25. 4 gpio24_in r - the pin stat us of atxpg_in/gpio24. 3 reserved r - reserved 2 gpio22_in r - the pin stat us of pcirst3#/gpio22. 1 gpio21_in r - the pin stat us of pcirst2#/gpio21. 0 gpio20_in r - the pin stat us of pcirst1#/gpio20. gpio2 drive enable register ? index d3h bit name r/w default description 7 gpio27_drv_en r/w 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode. 6 gpio26_drv_en r/w 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 0 0: gpio24 is open drain in output mode. 1: gpio24 is push pull in output mode. 3 reserved r/w 0 reserved 2 gpio22_drv_en r/w 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode. 0 gpio20_drv_en r/w 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode.
july, 2008 v0.29p 92 F71863 8.8.4 gpio3 registers gpio3 output enable register ? index c0h bit name r/w default description 7-4 reserved - - reserved. 3 gpio33_oe r/w 0 0: gpio33 is in input mode. 1: gpio33 is in output mode. 2 gpio32_oe r/w 0 0: gpio32 is in input mode. 1: gpio32 is in output mode. 1 gpio31_oe r/w 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. 0 gpio30_oe r/w 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. gpio3 output data register ? index c1h bit name r/w default description 7-4 reserved - - reserved. 3 gpio33_val r/w 1 0: gpio33 out puts 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w 1 0: gpio32 out puts 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w 1 0: gpio31 out puts 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w 1 0: gpio30 out puts 0 when in output mode. 1: gpio30 outputs 1 when in output mode. gpio3 pin status register ? index c2h bit name r/w default description 7-4 reserved - - reserved. 3 gpio33_in r - the pin stat us of rsmrst#/gpio33. 2 gpio32_in r - the pin st atus of pwrok/gpio32. 1 gpio31_in r - the pin status of ps_on#/gpio31. 0 gpio30_in r - the pin st atus of s3#/gpio30. gpio3 drive enable register ? index c3h bit name r/w default description 7-4 reserved - - reserved. 3 gpio33_drv_en r/w 0 0: gpio33 is open drain in output mode. 1: gpio33 is push pull in output mode. 2 gpio32_drv_en r/w 0 0: gpio32 is open drain in output mode. 1: gpio32 is push pull in output mode. 1 gpio31_drv_en r/w 0 0: gpio31 is open drain in output mode. 1: gpio31 is push pull in output mode.
july, 2008 v0.29p 93 F71863 0 gpio30_drv_en r/w 0 0: gpio30 is open drain in output mode. 1: gpio30 is push pull in output mode. 8.8.5 gpio4 registers gpio4 output enable register ? index b0h bit name r/w default description 7-4 reserved - - reserved. 3 gpio43_oe r/w 0 0: gpio43 is in input mode. 1: gpio43 is in output mode. 2 gpio42_oe r/w 0 0: gpio42 is in input mode. 1: gpio42 is in output mode. 1 gpio41_oe r/w 0 0: gpio41 is in input mode. 1: gpio41 is in output mode. 0 gpio40_oe r/w 0 0: gpio40 is in input mode. 1: gpio40 is in output mode. gpio4 output data register ? index b1h bit name r/w default description 7-4 reserved - - reserved. 3 gpio43_val r/w 1 0: gpio43 out puts 0 when in output mode. 1: gpio43 outputs 1 when in output mode. 2 gpio42_val r/w 1 0: gpio42 out puts 0 when in output mode. 1: gpio42 outputs 1 when in output mode. 1 gpio41_val r/w 1 0: gpio41 out puts 0 when in output mode. 1: gpio41 outputs 1 when in output mode. 0 gpio40_val r/w 1 0: gpio40 out puts 0 when in output mode. 1: gpio40 outputs 1 when in output mode. gpio4 pin status register ? index b2h bit name r/w default description 7-4 reserved - - reserved. 3 gpio43_in r - the pin status of irrx/gpio43 2 gpio42_in r - the pin status of irtx/gpio42. 1 gpio41_in r - the pin status of fanctrl3/gpio41. 0 gpio40_in r - the pin st atus of fanin3/gpio40. gpio4 drive enable register ? index b3h bit name r/w default description 7-4 reserved - - reserved. 3 gpio43_drv_en r/w 0 0: gpio43 is open drain in output mode. 1: gpio43 is push-pull in output mode. 2 gpio42_drv_en r/w 0 0: gpio42 is open drain in output mode. 1: gpio42 is push-pull in output mode.
july, 2008 v0.29p 94 F71863 1 gpio41_drv_en r/w 0 0: gpio41 is open drain in output mode. 1: gpio41 is push-pull in output mode. 0 gpio40_drv_en r/w 0 0: gpio40 is open drain in output mode. 1: gpio40 is push-pull in output mode.
july, 2008 v0.29p 95 F71863 8.9 vid registers (cr07) 8.9.1 vid configuration registers vid device enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 vid_en r/w 0 0: disable vid. 1: enable vid. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of vid base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of vid base address. 8.9.2 device registers 8.9.2.1 configuration register ? index 00h ( * cleared by slotocc_n and watch dog timeout) bit name r/w default description 7 wdout_en r/w 0 if this bit is set to 1 and watchdog timeout event occurs, wdtrst# output is enabled. 6-3 reserved - 0 return 0 when read. 2* otf_en r/w 0 this bit is used to enable vid on-the-fly function. 1:0 dummy reg r/w 0 dummy register. 8.9.2.2 vid offset register 0 ? index 01h bit name r/w default description 7:4 reserved r - reserved 3-0 vid_offset r/w 0 vid offset. vid_offset[3] is sign bit. 8.9.2.3 vid manual register ? index 02h bit name r/w default description 7* manual_mode r/w 0 if this bit is set to 1 and otf_en is 0, vidout will be vid_manual 6 key_ok r - this bit is 1 represents that the serial key is entered correctly. 5-4 reserved r - return 0 when read. 3-0 vid_manual r/w 0 manually assigned vidout value 8.9.2.4 serial key data register ? index 03h bit name r/w default description
july, 2008 v0.29p 96 F71863 7-0 key_data r/w 0 write serial data to this register co rrectly, the key_ok bit will be set to 1. hence, users are able to write key pr otected registers. the sequence to enable key_ok is 0x32, 0x5d, 0x42, 0xac. when key_ok is set, write this register 0x35 will clear key_ok. 8.9.2.5 vidin register ? index 04h ( * cleared by slotocc_n and watch dog timeout) bit name r/w default description 7-4 reserved r 0 reserved 3-0 vid_in r - return the vid_in status. 8.9.2.6 watchdog timer configuration register 1 ? index 05h bit name r/w default description 7 reserved r 0 reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1:0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec 8.9.2.7 watchdog timer configuration register 2 ? index 06h bit name r/w default description 7:0 wd_time r/w 0 time of watchdog timer 8.9.2.8 output voltage control register 1 ? index 07h ( * cleared by slotocc_n and watch dog timeout) bit name r/w default description 7-6 dummy reg r/w 0 dummy register. 5 reg_rst_sel r/w 0 0: the vid registers is reseted when vdd power lose and watch dog timeout. 1: the vid registers is reseted by slotcc_n and watch dog timeout. 4 reserved r/w 0 reserved 3-0 dummy reg r/w 0 dummy registers.
july, 2008 v0.29p 97 F71863 8.10 spi registers (cr08) 8.10.1 configuration register spi control register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 sptie r/w 0 spi interrupt enable. set to 1, spie interrupt enabled, set to 0 spie interrupt disabled. 4 mstr r/w 1 master mode select. set to 1, spi function is master mode; set to 0 is disable spi function 3 cpol r/w 0 clock polarity this bit selects inverted or non-inverted spi clo ck. set to 1, active low clock selected; sck idles high. set to 0, active high clock selected; sck idles low. 2 cpha r/w 0 clock phase. this bit is used to shift the sck serial clock. set to 1, the first sck edge is issued at the beginning of the transfer operation. set to 0, the first sck edge is issued one-half cycle into the transfer operation. 1 reserved - 0 reserved 0 lsbfe r/w 0 this bit control data shift from lsb or msb. set to 1, data is transferred from lsb to msb. set to 0, data is transferred from msb to lsb. spi timeout register ? index f1h bit name r/w default description 7-0 timer_val r/w 8?h04 the time in second to assert fwh_dis signal when spi in used as backup bios. spi baud rate divisor register ? index f2h bit name r/w default description 7-3 reserved - 0 reserved 2-0 baud_val r/w 1 this register decides to sck frequency. baud rate divisor equation is 33mhz/2*(baud_val). 00: 33mhz. 01: 16.7mhz. spi status register ? index f3h bit name r/w default description 7 spie r/w 0 spi interrupt status. when spi is transferred or received data from device finish, this bit will be set. write 1 to clear this bit. 6 fwh_dis r/w - when spi is used as backup bios, this bit will set when time in second reaches the value programmed in timer_val (crf1). write one to clear this register. when spi is used as primary bios, th is register will always be 1. 5 spe r - this bit reflects the spi_en register. (which will be 1 when spi is enabled.) 4 spi0_timer_dis r/w - when spi is used as primary bios, it will also have backup function as used in backup bios. the bit will set to 1 when the time in second reaches the value programmed in timer_val (crf1). that is the first spi could not function well. then a reset signal will asserted and reboot the system with the second spi. (i could be another spi with chip-s elected by fwh_dis or another 4mbits of an 8mbits spi. the spi_cs1_en (cr2 d[4]) determines the method). write one to clear this bit.
july, 2008 v0.29p 98 F71863 3 sptef r 0 spi operation status. when spi is transferred or received data from device, this bit will be set 1, clear by spi operation finish. 2-0 reserved - - reserved spi high byte data register ? index f4h bit name r/w default description 7-0 h_data r 0 when spi is received 16 bits data from device. this register saves high byte data. spi command data register ? index f5h bit name r/w default description 7-0 cmd_data r/w 0 this register provides command value for flash command. spi chip select register ? index f6h bit name r/w default description 7-4 reserved - - reserved 3 dummy_reg r/w 0 dummy register. 2 dummy_reg r/w 0 dummy register. 1 dummy_reg r/w 0 dummy register. 0 cs0 r/w 0 chip select 0. to select device 0 spi memory mapping register ? index f7h bit name r/w default description 7-3 reserved - 0 reserved 2-0 mem_map r/w - this register decides memory size. 3?b000: one of the memory sizes is 512k bytes. 3?b001: one of the memory sizes is 1024k bytes. 3?b100: one of the memory sizes is 2048k bytes. 3?b011: one of the memory sizes is 4096k bytes. 3?b100: one of the memory sizes if 8092k bytes. spi operate register ? index f8h bit name r/w default description 7 type r/w 0 this bit decide flash continuous pr ogramming mode. set to 1, if programming continuous mode is same as the sst flas h. set to 0 if programming continuous mode is same as the atmel flash 6 io_spi r/w 0 this bit control spi function tr ansfer 8 bit command to device. clear 0 by operation finish. 5 rdsr r/w 0 this bit control spi function read st atus from to device. clear 0 by operation finish. 4 wrsr r/w 0 this bit control spi function write status to device. clear 0 by operation finish. 3 sector_erase r/w 0 this bit control spi function se ctor erase device. clear 0 by operation finish. 2 read_id r/w 0 this bit control spi function re ad id from device. clear 0 by operation finish.
july, 2008 v0.29p 99 F71863 1 prog r/w 0 this bit control spi function program data to device or set to 1 when memory cycle for lpc interface program flash. clear 0 by operation finish. 0 read r/w 0 this bit control spi function read data from device or set to 1 when memory cycle for lpc interface read flash. clear 0 by operation finish. spi low byte data register ? index fah bit name r/w default description 7-0 l_data r 0 when spi is received 16 bits or 8 bits data from device. this register saves low byte data. spi address high byte register ? index fbh bit name r/w default description 7-0 addr_h_byte r/w 0 this regist er provides high byte address for sector erase, program, read operation. spi address medium byte register ? index fch bit name r/w default description 7-0 addr_m_byte r/w 0 this register provides medium byte addres s for sector erase, program, read operation. spi address low byte register ? index fdh bit name r/w default description 7-0 addr_l_byte r/w 0 this regist er provides low byte address for sector erase, program, read operation. spi program byte register ? index feh bit name r/w default description 7-0 porg_byte r/w 0 this regi ster provides number to program flash for continuous mode. spi write data register ? index ffh bit name r/w default description 7-0 wr_dat r/w 0 this register provides data to write flash for program, write status function.
july, 2008 v0.29p 100 F71863 8.11 pme and acpi registers (cr0a) 8.11.1 configuration register device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable register ? index f0h bit name r/w default description 7 reserved - - reserved 6 mo_pme_en r/w 0 mous e pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 5 kb_pme_en r/w 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 4 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 3 prt_pme_en r/w 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 2 ur2_pme_en r/w 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event. 1 ur1_pme_en r/w 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event. 0 fdc_pme_en r/w 0 fdc pme event enable. 0: disable fdc pme event. 1: enable fdc pme event. pme event status register ? index f1h bit name r/w default description 7 reserved - - reserved 6 mo_pme_st r/w - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. writ e 1 to clear to be ready for next pme event. 5 kb_pme_st r/w - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event.
july, 2008 v0.29p 101 F71863 4 hm_pme_st r/w - hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 3 prt_pme_st r/w - parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ur2_pme_st r/w - uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ur1_pme_st r/w - uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 fdc_pme_st r/w - fdc pme event status. 0: fdc has no pme event. 1: fdc has a pme event to assert. write 1 to clear to be ready for next pme event. acpi control register ? index f4h bit name r/w default description 7 ts3 r/w 0 set to 1 into s1 state. two wake up methods: 1. pme wake up event ( must write this bit to 0. 2. ps_out# wake up event ( auto clear this bit. 6 spi_rst_en r/w 0 set one to enable the reset signal from spi via the pwrok or pcirst#. (spi as backup bios w ill assert a reset signal when fwh doesn?t response in 4 seconds) 5 key_sel_add r/w 0 set this bit one a nd key_sel (cr2d[2:1]) 2?b00 will select windows 98 wakeup key as keyboard wakeup key. 4 en_kbwakeu p r/w 0 set one to enable keyboard wakeup event asserted via pwsout#. 3 en_mowakeu p r/w 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : reserved (always on) 11: always off 0 vsb_pwr_los s r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it acpi control register ? index f5h bit name r/w default description
july, 2008 v0.29p 102 F71863 7 sel_s3 r/w 0 1:selected by ts3 ts3 0: chip decided into s3 state from s3 pin 1 : chip direct into s3 state 0: chip decided into s3 state from vdd (vcc) power detect ok., which chip detects voltage circuit 6 reserved r/w 0 dummy register 5 rstcon_en r/w 0 0: enable rstcon# output via pwrok. 1: enable rstcon# output via pcirst#. 4-3 delay r/w 11 the pwrok delay timing from vdd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2 vindb_en r/w 1 enable the pc irstin_n and atxpwgd de-bounce. 1 pcirst_db_en r/w 0 enab le the lreset_n de-bounce. 0 reserved r/w 0 dummy register. acpi control register ? index f7h bit name r/w default description 7-4 reserved r/w 0 reserved. 3-2 reserved r/w 0 dummy registers. 1 pwr_sts2_tri r/w 0 set this bit to one will c uase pin55 be tri-state status in s5 state. 0 pwr_sts_en r/w 1 enable power status pins. pin77 will be s5# function. p56 will be st1 function. p55 will be st2 function.
july, 2008 v0.29p 103 F71863 9. electron characteristic 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to 70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device 9.2 dc characteristics (t a = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v ) parameter conditions min typ max unit temperature error, remote diode 60 o c < t d < 145 o c, vcc = 3.0v to 3.6v 0 o c july, 2008 v0.29p 104 F71863 input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/ood 12t -ttl level bi-directional pin, output pin with 12ma source-sink capability, and can programming to open-drain function. input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol -12 -9 ma vol = 0.4 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o 12t - ttl level bi-directional pin, output pin with 12ma source-sink capability. input low threshold voltage vt- 0.6 v vdd = 3.3 v input high threshold voltage vt+ 0.9 v vdd = 3.3 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = 1.2v input low leakage ilil -1 a vin = 0v in ts - ttl level input pin with schmitt trigger input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v in t5v - ttl level input pin with 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v in ts5v - ttl level input pin with schmitt trigger, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v od 12 -open-drain output with12 ma sink capability. output low current iol -12 ma vol = 0.4v od 12-5v -open-drain output with12 ma sink capability, 5v tolerance. output low current iol -12 ma vol = 0.4v od 24 -open-drain output with 24 ma sink capability. output low current iol -24 ma vol = 0.4v od 16-u10-5v -open-drain output with 16 ma sink capability, pull-up 10k ohms, 5v tolerance. output low current iol -16 ma vol = 0.4v o 8 - output pin with 8 ma source-sink capability. output high current ioh +6 +8 ma voh = 2.4v o 8-u47-5v - output pin with 8 ma source-sink capability, pull-up 47k ohms, 5v tolerance. output high current ioh +6 +8 ma voh = 2.4v o 12 - output pin with 12 ma source-sink capability. output high current ioh +9 +12 ma voh = 2.4v o 30 - output pin with 30 ma source-sink capability. output high current ioh +26 +30 ma voh = 2.4v
july, 2008 v0.29p 105 F71863 10. ordering information 11. package dimensions 128 pqfp part number package type production flow F71863fg 128-pqfp green package commercial, 0 c to +70 c feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications ar e subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
july, 2008 v0.29p 106 F71863 12. F71863 application circuit densel# moa# index# drva# step# dir# wpt# rdata# wdata# wgate# tr k0# vcc3v dskchg# hdsel# pwok rsmrst# vsb3v r106 4.7k r107 4.7k rsmrst# and pwrok pull-up lreset# tr k0# dsr2# rts2# dtr2# sin2 sout2 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 j1 header 17x2 vsb3v index# vsb3v r11 4.7k slotocc# tit le size document number rev date: sheet of F71863f&fdd 0.11 feature integration technology inc. b 17 monday , july 21, 2008 kdat kclk md at mc lk pwok led_vcc cpu_pwrgd ovt# pwsin# pwsout# s3# pson# pcirst3# s5# atxpg_in pme# pcirst1# pcirst2# sout2 vcc3v vcc3v r6 1k vcc3v r6 off: fan start duty 60% on: fan start duty 100% r7 off: spi back-up on: spi primary r8 off: pwm fan on: linear fan r9 off: 4e on: 2e r10 off: spi_disable on: spi_enable wpt# s3 irrx irtx densel# st1 & st2 pull-up r floppy conn. fanin1 r4 1k r1 1k r3 1k r2 1k r5 1k vcc5v wpt# rdata# tr k0# index# dskchg# vbat slot_occ# fanctl1 drva# 1 2 c1 0.1u (place capacitor close to ic) vsb3v dtr2#/fwh_trap 1 rts2#/pwm_dc 2 dsr2# 3 vcc 4 sout2/spi_trap 5 sin2 6 densel# 7 moa# 8 drva# 9 wdata# 10 dir# 11 step# 12 hdsel# 13 wgate# 14 rdata# 15 trk0# 16 index# 17 wpt# 18 dskchg# 19 gnd 20 fanin1 21 fanctl1 22 fanin2 23 fanctl2 24 fanin3/gpio40 25 fanctl3/gpio41 26 irtx/gpio42 27 irrx/gpio43 28 lreset# 29 ldrq# 30 serirq 31 lfram# 32 lad0 33 lad1 34 lad2 35 lad3 36 vcc 37 pciclk 38 gpio15/led_vsb/alert# 64 gpio14/fwh_dis/wdtrst#/spi_cs1# 63 gpio13/spi_mosi/beep 62 gpio12/spi_miso/fanctl1_1 61 gpio11/spi_cs0 60 gpio10/spi_clk 59 peci/amdsi_dat 58 amdsi_clk 57 st1/gpio03/wdtrst# 56 st2/slotocc#/gpio02 55 vdimm_en 54 vdda_en 53 vidoutd 52 vidoutc 51 vidoutb 50 vidouta 49 gnd 48 vldt_en 47 vcore_en 46 vidind 45 vidinc 44 vidinb 43 vidina 42 ga20 41 kbrst# 40 clkin 39 busy 102 pe 101 slct 100 vcc 99 vcore(vi n1) 98 vldt(vi n2) 97 vdda(vin3) 96 vdimm(vin4) 95 vin5 94 vin6 93 vref 92 d1+(cpu) 91 d2+ 90 d3+(system) 89 agnd(d-) 88 copen# 87 vbat 86 rsmrst#/gpio33 85 ps_on#/gpio31 83 s3#/gpio30 82 pwsout#/gpio27 81 pwsin#/gpio26 80 pme#/gpio25 79 atxpg_in/gpio24 78 s5# 77 pcirst3#/gpio22 76 pcirst2#/gpio21 75 pcirst1#/gpio20 74 gnd 73 mclk 72 mdata 71 kclk 70 kdata 69 vsb 68 ovt# 67 cpu_pwrgd 66 gpio16/led_vcc 65 ack# 103 slin# 104 init# 105 err# 106 afd# 107 stb# 108 pd0 109 pd1 110 pd2 111 pd3 112 pd4 113 pd5 114 pd6 115 pd7 116 gnd 117 dcd1# 118 ri1# 119 cts1# 120 dtr1#/fan60_100 121 rts1# 122 dsr1# 123 sout1/conf ig4e_2e 124 sin1 125 dcd2# 126 ri2# 127 cts2# 128 pwok/gpio32 84 F71863fg u1 r92 4.7k step# vcc3v 1 2 c3 0.1uf pciclk dtr2# vcc3v vsb3v 1 2 c4 0.1u lad3 r93 4.7k sout1 1 2 c2 0.1u vcc3v 1 2 c5 0.1u vbat (gnd close to ic) lad2 rts2# dtr1# lad1 fwh_dis led_vsb sck spi_cs0# mi so mosi moa# gpio03 amdsi_clk peci/amdsi_dat dskchg# hdsel# lad0 slotocc# clk_24/48m kbrst# ga20 slotocc#_cpu cts2# dtr1# cts1# ri1# dcd1# dir# sin1 sout1 dsr1# rts1# ri2# dcd2# lframe# fanctl2 fanin2 pd7 ack# pd4 init# slin# pd5 pd6 pd0 stb# afd# err# pd3 pd2 pd1 vidoutc vidoutd vdda_en vdimm_en vidouta vidoutb atxpg_in serirq wgate# slotocc# ldrq# r8 1k r9 1k r7 1k power-on trip r10 1k gpio03 fanin3 fanctl3 vdda(vin3) vcore(vin1) vldt(vin2) slct rsmrst# d3+ d- pe copen# vref d1+ d2+ busy vdimm(vin4) vin5 vin6 rdata# vcore_en vldt_en vidind vidina vidinb vidinc wdata#
july, 2008 v0.29p 107 F71863 slct busy pe 1 2 3 4 5 6 7 8 rn5 33-8p4r 1 2 3 4 5 6 7 8 rn6 33-8p4r 1 2 3 4 5 6 7 8 rn7 33-8p4r dsr2# rts2# dtr2# sin2 sout2 mc lk kdat kclk md at 1 2 3 4 5 6 7 8 rn2 2.7k-8p4r 1 2 3 4 5 6 7 8 rn4 2.7k-8p4r ring-in wake-up not supported by F71863. please use chipset ring-in for wake-up function vcc5v/3v 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j2 db25 1 2 3 4 5 6 7 8 rn3 2.7k-8p4r 1 2 3 4 5 6 7 8 rn1 2.7k-8p4r cts1# ri1# dcd1# cts2# sout1 dsr1# rts1# dtr1# ri2# dcd2# sin1 vcc5v r12 2.7k c25 100p r13 4.7k r14 4.7k f2 fuse c26 0.1u l1 fb l3 fb c24 100p 1 2 3 4 5 6 js1 m-din_6-r r15 4.7k l2 fb c27 100p 1 2 3 4 5 6 js2 m-din_6-r c29 0.1u c28 100p l4 fb f1 fuse 1 2 3 j3 con3 r16 4.7k ps2 keyboard interface ps2 mouse interface vsb5v rin2 -12v dtrn2 dsrn2 rtsn2 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u3 ctsn2 sinn2 gnd vcc5v soutn2 ctsn2 dcdn2 soutn2 dcdn2 sinn2 dsrn2 rtsn2 5 9 4 8 3 7 2 6 1 p2 uart db9 dtrn2 rin2 +12v 1 2 d1 1n5819 vcc5v pd7 ack# pd4 init# slin# pd6 pd5 pd0 stb# afd# err# pd3 pd2 pd1 tit le size document number rev date: sheet of printer &uart 0.11 feature integration technology inc. b 27 friday , may 02, 2008 c22 180p c6 180p parallel port interface c14 180p for lekage to power c7 180p c15 180p (female) c8 180p c16 180p dtrn1 dsrn1 sinn1 ctsn1 gnd rtsn1 dcdn1 1 2 3 4 5 jp1 header 5 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u2 c9 180p soutn1 ctsn1 dsrn1 dtrn1 dcdn1 5 9 4 8 3 7 2 6 1 p1 uart db9 sinn1 c17 180p rtsn1 soutn1 c10 180p c18 180p uart 1 port interface c11 180p uart 2 port interface c19 180p c12 180p c20 180p c13 180p c23 0.1u rin1 rin1 ir interface c21 180p -12v +12v vcc5v irtx irrx
july, 2008 v0.29p 108 F71863 t rt2 th er mi stor 10k 1% r33 10k 1% (for system) t rt3 th er mi stor 10k 1% vref d1+ d2+ d3+ vcc3v r27 4.7k c33 3300p vcc3v r25 4.7k vref vref d1+ d2+ d3+ t rt1 th er mi stor 10k 1% r30 10k 1% r36 1k vdimm vdda(vin3) vdda r38 10k vdimm(vin4) r37 10k copen# r39 10k r108 10k +12v vin6 vin5 r109 10k vldt(vin2) vcore(vin1) r110 20k the best voltage input level is about 1v. r111 200k vldt r112 1k *vin1 vin2 vin3 vin4 internal pull-down 225k ohm vcore vcc1.5v fwh_dis sck spi_cs0# miso mosi chipset_pwrok ovt# r35 4.7k vcc3v r28 4.7k r94 0 q 2 s# 1 w# 3 vss 4 vcc 8 c 6 hold# 7 d 5 u4 spi flash memory ovt pull-up chipset_reset d- vcc3v r95 0 d- d- r17 2m c31 1000p 1 2 sw1 vbat voltage sensing. th er md a th er md c vsb3v q13 r99 4.7k vsb5v pled led_vsb led_vcc r100 4.7k q14 vsb5v vsb3v r101 4.7k r102 4.7k susled c32 3300p c30 3300p q2 pnp 3906 q1 pnp 3906 tit le size document number rev date: sheet of hardware monitor, spi flash 0.11 feature integration technology inc b 37 monday , july 21, 2008 case open circuit from cpu diode sensing circuit (for system) thermistor sensing circuit for system temperature sensing for system q3 mosf et n c34 1uf r34 100k back_up bios reset circuit r32 10k 1% (for system)
july, 2008 v0.29p 109 F71863 fanctl2 r52 4.7k fanctl3 r64 4.7k fanctl3 vcc3v r103 4.7k vcc3v r104 4.7k r105 4.7k c42 0.1u r58 10k r56 27k r51 4.7k q7 pnp r50 4.7k r53 4.7k + c39 47u +12v 1 2 3 jp4 header 3 r55 330 q9 mosfet n 2n7002 d4 1n4148 c45 0.1u r69 10k fanctl1 r68 27k r63 4.7k q10 pnp r62 4.7k r65 4.7k + c43 47u +12v 1 2 3 jp6 header 3 r67 330 q12 mosfet n 2n7002 d6 1n4148 1 2 3 4 jp2 4 header vcc5v r40 4.7k r49 10k r41 27k r42 10k +12v + c35 47u d2 1n4148 c36 0.1u fanin1 r48 100 (4 pin fan control) fanctl1 tit le size document number rev date: sheet of fan control 0.11 feature integration technology inc. b 47 friday , may 02, 2008 pwm fan 3 speed control pwm fan 1 speed control pwm fan 2 speed control r46 3.9k r45 10k dc fan control with op 1 r59 10k 1 2 3 jp5 con3 fanin1 r60 3.9k r61 10k d5 1n4148 5 6 7 8 4 + - u5b lm358 dc fan control with op 2 r57 27k 12v r54 4.7k c40 47u q8 pmos c41 0.1u fanin2 12v q11 pmos r66 4.7k d7 1n4148 dc fan control with op 3 1 2 3 jp7 con3 12v c46 0.1u c44 47u r73 10k r70 10k r72 3.9k r71 27k 3 2 1 8 4 + - u6a lm358 fan control for pwm or dc fanin2 fanin3 q6 pmos fanin3 r44 27k 1 2 3 jp3 con3 r47 10k d3 1n4148 r43 4.7k c37 47u c38 0.1u 3 2 1 8 4 + - u5a lm358 fanctl2
july, 2008 v0.29p 110 F71863 vidoutc vidoutd vidouta vidoutb vidind vidina vidinb vidinc r78 4.7k r79 4.7k r80 4.7k r81 4.7k vcc3v cpu pwm controller tit le size document number rev date: sheet of vid 0.11 feature integration technology inc. b 57 friday , may 02, 2008 r74 4.7k r77 4.7k r75 4.7k r76 4.7k vcc3v
july, 2008 v0.29p 111 F71863 vcc3v vcc3v vsb3v power sequence pull-up r client peci_client peci client r82 300 amdsi r83 300 vddio sid sic r84 100k 2.5v r98 4.7k cpu_pwrgd cpu_pwrgd pull-up amdsi_clk vldt_en vdimm_en vdda_en vcore_en r85 4.7k r88 4.7k r96 4.7k r97 4.7k peci/amdsi_dat peci/amdsi_dat (avoid pre-bios floating) tit le size document number rev date: sheet of amdsi/peci 0.11 feature integration technology inc. a 67 friday , may 02, 2008 vcc3v
july, 2008 v0.29p 112 F71863 pcirst2# pcirst3# 1 2 1k sata*2 pci front panel F71863 ata 133 ide atx connector cpu north bridge south bridge pclk_1,2,3(33mhz) vcc3 1 2 r90 4.7k vsb5 1 2 tc 1 22uf 3v3 11 -12v 12 gnd 13 ps-on 14 gnd 15 gnd 16 gnd 17 -5v 18 5v 19 5v 20 3v3 1 3v3 2 gnd 3 5v 4 gnd 5 5v 6 gnd 7 pw-ok 8 5vsb 9 12v 10 atx1 atx connector vcc3 vcc5 vsb5 +12v vcc5 -12v 1 2 r86 4.7k vsb3 1 2 r91 4.7k vsb5 lreset# -pwr_btn 2 1 c47 0.1uf rstgnd 5 reset 7 psw+ 6 psw- 8 front panel 1 2 r87 3 4 4.7k 1 2 4.7k vsb3 pcirst3# pcirst2# tit le size document number rev date: sheet of example_acpi 0.11 feature integration technology inc. a 77 friday , may 02, 2008 pcirst1# pson# pwsout# atxpg_in rsmrst# pwsin# s3#

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